\ Do not use this file except in compliance with the License. You may \ obtain a copy of the License at http://www.microcore.org/License/ \ Software distributed under the License is distributed on an "AS IS" basis, \ WITHOUT WARRANTY OF ANY KIND, either express or implied. \ See the License for the specific language governing rights and limitations \ under the License. \ \ The Original Code is: IMAGES.FS \ \ Last change: KS 18.02.2013 12:41:44 \ \ The Initial Developer of the Original Code is Klaus.Schleisiek AT microcore.org. \ Port to the gforth system, extensions and adding the debugger by Ulrich.E.Hoffmann AT xlerb.de \ \ MicroCore saving the target image in different formats Only Forth also definitions : Bin-file ( -- ) \ write program memory image to file as binary BL word dup c@ 0= abort" file name required" count R/W BIN Create-file abort" File could not be created" >r 0 >memory there cells r@ write-file abort" File write error" r> close-file abort" File close failed" ; : Byte-file ( -- ) \ write program memory image to file as byte oriented binary BL word dup c@ 0= abort" file name required" count R/W BIN Create-file abort" File could not be created" there 0 ?DO I >memory @ pad c! dup pad 1 rot write-file abort" File write error" LOOP close-file abort" File close failed" ; \ -------------------------------------------------------------- \ Create bootable code for 8-bit EEPROM \ -------------------------------------------------------------- $C20001 Constant Polynom ( x24+x23+x22+x17 maximum period CRC ) : crc-step ( w crc1 -- w' crc2 ) 2dup xor $800000 and >r 2* swap 2* swap r> IF Polynom xor THEN ; : crc ( crc1 u -- crc2 ) &16 lshift swap &7 FOR crc-step NEXT $FFFFFF and nip ; : crc-check ( addr length -- crc ) 0 -rot 1- FOR dup >r @ crc r> 1+ NEXT drop ; : pack_image ( -- addr ) Pad dup cell+ 0 0 >memory there cells bounds DO I c@ swap >r swap >r r@ c! r> 1+ r> 1+ 1 cells +LOOP swap >r over cell+ over crc-check unpack unpack r@ c! r@ 1+ c! r> 2 + c! over ! ; : CRC-file ( -- ) \ write program memory image length field and CRC BL word dup c@ 0= abort" file name required" count R/W BIN Create-file abort" File could not be created" pack_image dup @ 7 + bounds ?DO dup I 1 rot write-file abort" File write error" LOOP close-file abort" File close failed" ; \ 32-bit length-field | program image | 3 byte crc \ -------------------------------------------------------------- \ Create VHDL output files for the object code \ -------------------------------------------------------------- : makeopcode ( opcode -- string ) Base save binary 0 <# # # # # # # # # #> ; : writeclause ( handle addr -- ) count rot write-file abort" File write error" ; : file>here ( string -- addr len ) count r/o open-file abort" PROLOG/EPILOG file not present" >r here 2000 r@ read-file abort" PROLOG/EPILOG: could not read" here swap r> close-file drop ; \ -------------------------------------------------------------- \ Create VHDL boot rom code via case statement \ -------------------------------------------------------------- Create romclause ," WHEN 16#0000# => RETURN _00000000_; " : >romclause ( offset -- addr ) romclause + 6 + ; char " $19 >romclause c! char " $22 >romclause c! #cr $24 >romclause c! #lf $25 >romclause c! 9 Constant vhdladdr $1A Constant vhdlcode : makeaddr ( addr -- string ) temp_hex 0 <# # # # # #> ; : make_whenclause ( caddr -- ) dup makeaddr vhdladdr >romclause swap cmove >memory @ makeopcode vhdlcode >romclause swap cmove ; Create prolog ," prolog.vhd" Create epilog ," epilog.vhd" : VHDL-file ( -- ) BL word dup c@ 0= abort" file name required" count R/W BIN create-file abort" File could not be created" >r prolog file>here r@ write-file abort" PROLOG write error" r> 0 there bounds DO I make_whenclause dup romclause writeclause LOOP >r epilog file>here r@ write-file abort" EPILOG write error" r> close-file abort" File close failed" ; Create boot_prolog ," boot_prolog.vhd" : Boot-file ( -- ) BL word dup c@ 0= abort" file name required" count R/W BIN create-file abort" File could not be created" >r boot_prolog file>here r@ write-file abort" PROLOG write error" r> 0 there bounds DO I make_whenclause dup romclause writeclause LOOP >r epilog file>here r@ write-file abort" EPILOG write error" r> close-file abort" File close failed" ; \ ---------------------------------------------------------------------- \ Create internal VHDL memory code for preconfig internal RAM simulation \ ---------------------------------------------------------------------- Create clause ," _00000000_, " : >clause ( offset -- addr ) clause + ; char " $1 >clause c! char " $A >clause c! #cr $C >clause c! #lf $D >clause c! $2 Constant vhdlcode : make_initstring ( caddr -- ) >memory @ makeopcode vhdlcode >clause swap cmove ; Create internal_prolog ," prolog_internal.vhd" Create internal_epilog ," epilog_internal.vhd" : Prog-file ( -- ) BL word dup c@ 0= abort" file name required" count R/W BIN create-file abort" File could not be created" >r internal_prolog file>here r@ write-file abort" PROLOG write error" r> 0 there bounds DO I make_initstring dup Clause writeclause LOOP >r internal_epilog file>here r@ write-file abort" EPILOG write error" r> close-file abort" File close failed" ; \ -------------------------------------------------------------- \ Create Xilinx MEM File for block ram initialization \ -------------------------------------------------------------- : placeaddr ( addr padaddr -- addr paddr+ ) \ >r dup 0 <# # # # # [char] @ hold #> r> 2dup + >r swap cmove r> \ Xilinx format >r dup 0 <# [char] : hold BL hold # # # # #> r> 2dup + >r swap cmove r> \ Lattice format ; : placebyte ( caddr padaddr -- caddr+ padaddr+ ) >r dup 1+ swap opcode@ 0 <# # # BL hold #> r> 2dup + >r swap cmove r> ; : make_romline ( caddr -- caddr+ saddr slen ) temp_hex here placeaddr $10 0 DO placebyte LOOP #cr over c! 1+ #lf over c! 1+ here tuck - ; : MEM-file ( -- ) BL word dup c@ 0= abort" file name required" count R/W BIN create-file abort" File could not be created" >r 0 BEGIN make_romline r@ write-file abort" File write error" dup there u> UNTIL drop r> close-file abort" File close failed" ; T definitions h' VHDL-file Alias VHDL-file Host