\
\ Last change: KS 31.10.2015 19:57:12
\
\ MicroCore load screen for coretest simulation.
\ It produces a VHDL-file that models the program memory.
\
Only Forth also definitions hex

[IFDEF] empty unpatch empty [ENDIF] Marker empty

include gforth-config.fs        \ Some System word (re)definitions for a more sympathetic environment
include vhdl.fs                 \ simple VHDL interpreter for constants
include ../uCore/constants.vhd
include microcore.fs            \ the cross-compiler
include images.fs               \ object code output files
include disasm.fs               \ the disassembler
include constants.fs            \ MicroCore Register addresses and bits

new Target                      \ reset target compiler and go into target compilation mode

9 trap-addr code-origin
          0 data-origin

Variable Dp  \ must be set to the value of Tdp in the cold boot routine
: d+      ( d1 d2 -- d3 )       >r swap >r +  r> r> +c ;
: d-      ( d1 d2 -- d3 )       >r swap >r -  r> r> invert +c ;
: um/mod  ( ud u  -- urem uquot )   udivide ;
WITH_MULT [IF] [ELSE] : um*     ( u1 u2 -- udprod )   umultiply ; [THEN]
: (do    ( limit start -- count end )  under - 1- swap 1- ;
Host: DO     ( n1 n2 -- )  ( R: -- n3 n4 )                 ?comp T (do >r FOR H ;
Host: LOOP   ( -- )  ( R: n1 n2 -- n1 n2 )  ( R: n1 0 -- ) ?comp T NEXT rdrop H ;
: erase   ( addr len -- )       0 ;noexit  \ fall into fill
: fill    ( addr len u -- )     swap >r swap 1- r> ?FOR  over swap 1 + st  NEXT  2drop ;
: sqrt    ( u -- urem uroot )   uroot ;
WITH_MULT [IF] : log2    ( u -- u' )  ulog ;  [THEN]

include coretest.fs

#reset TRAP: rst  ( -- ) coretest                ;  \ compile branch to TEST at reset vector location
#isr   TRAP: isr  ( -- ) intserver IRET          ;
#esr   TRAP: esr  ( -- ) r> 1- BRANCH            ;  \ retry instruction
#osr   TRAP: osr  ( n -- n' )  drop ovfl_pattern ;
WITH_BYTES [IF]
#asr   TRAP: asr  ( -- ) r> 1- addrtrap          ;
[THEN]

end

MEM-file           program.mem  .( sim_core.fs written to program.mem )