\ 
\ Last change: KS 02.11.2015 10:53:52
\
\ MicroCore load screen for simulation.
\ It produces a VHDL-file that models the program memory.
\
Only Forth also definitions hex

[IFDEF] empty unpatch empty [ENDIF] Marker empty

include gforth-config.fs        \ Some System word (re)definitions for a more sympathetic environment
include vhdl.fs                 \ simple VHDL interpreter for constants
include ../uCore/constants.vhd
include microcore.fs            \ the cross-compiler
include images.fs               \ object code output files
include disasm.fs               \ the disassembler
include constants.fs            \ MicroCore Register addresses and bits

new Target                      \ reset target compiler and go into target compilation mode

8 trap-addr code-origin
          0 data-origin

include forth.fs
include float.fs

: boot  ( -- )  &1000 r>t t>r 
   BEGIN REPEAT
;

#reset TRAP: rst  ( -- ) boot            ;  \ compile branch to TEST at reset vector location
#isr   TRAP: isr  ( -- ) ints@ drop IRET ;
#esr   TRAP: esr  ( -- ) r> 1- BRANCH    ;  \ retry instruction

end

MEM-file program.mem  .( sim.fs written to program.mem )