\
\ Last_change: KS 02.03.2013 12:31:39
\
\ MicroCore load screen for the core test program that is transferred
\ into the program memory via the debug umbilical
\
Only Forth also definitions hex

[IFDEF] empty unpatch close-port empty [ENDIF] Marker empty

include gforth-config.fs        \ Some System word (re)definitions for a more sympathetic environment
include vhdl.fs                 \ simple VHDL interpreter for constants
include ../uCore/constants.vhd
include microcore.fs            \ the cross-compiler
include disasm.fs               \ the disassembler
include umbilical.fs            \ defines the actual serial port used on this computer
include constants.fs            \ MicroCore Register addresses and bits

new Target                      \ reset target compiler and go into target compilation mode

8 trap-addr code-origin
          0 data-origin

include forth.fs
: pause ; \ include multitask.fs
include debugger.fs

: boot  ( -- )
   0 #top erase  CALL Initialisation
   init   debugService
;

#reset TRAP: rst   ( -- ) boot                   ;  \ compile branch to TEST at reset vector location
#isr   TRAP: isr   ( -- ) ints@ drop IRET        ;
#esr   TRAP: esr   ( -- ) r> 1- BRANCH           ;  \ retry instruction
#osr   TRAP: osr   ( -- )                        ;  \ ?OVFL Vektor
#break TRAP: break ( -- ) debugger               ;  \ Debugger
#data! TRAP: data! ( dp-1 n -- dp )  swap 1+ st  ;  \ Data memory initialisation
WITH_BYTES [IF]
#asr   TRAP: asr   ( -- ) r> 1- addrtrap         ;  \ misaligned address trap
[THEN]

end