*** uCore 1.90  08-Dec-2015 ks

Radical restructuring of the Kernel, making uBus THE central resource
in the design.

*** uCore 1.81  22-Nov-2015 ks

Minor modifications and renaming.

*** uCore 1.80  01-Nov-2015 ks

Radical redesign of uCore.vhd and the instruction set.
(Source code compatibility maintained.)

The tri-stateable data bus has been abandoned.

Barrel shifting realized using the multiplier, if present.

Consequently, a new set of shift instructions: SHIFT, ASHIFT, DSHIFT,
DASHIFT, which serve as primitives for 2/, and u2/.

Divide and multiply primitives now use DST_DOUT instead of R.TOR.

Repeat primitives >FOR <instruction> <NEXT implemented as a
side effect free alternative to TIMES in privious implementations. The
loop index resides in TOR. The sign of the loop index will be saved in
s.fwrd by >FOR and the default for s.fwrd = '1'.
So SHIFT, ASHIFT, DSHIFT, DASHIFT will shift left for positive indices,
and shift right for negative indices.

Radical redesign of the data memory interface, clearly separating
memory data input and output.

Floating point primitives implemented:
op_NORM, op_FMULT, op_FLOAT, op_INTEG, op_LOGS, and op_SQRTS

*** uCore 1.76  18-Jul-2015 ks

CONSTANT async_reset in FUNCTIONS.VHD selects the use of
synchronous or asynchronous reset for radiation critical applications.
uReg_read and uReg_write now return a straight boolean.

*** uCore 1.75  22-Apr-2015 ks

Redesign of internal_ram and external_ram, which can now be used
universally and initialized for simulation.
Bugfix in op_ADC without SAT_ARITH overflow setting.

*** uCore 1.74   1-Apr-2015 ks

Radical redesign of instruction decoding in uCore.vhd.
Also the opcode definition format in constants.vhd changed.
TIMES instruction removed.

*** uCore 1.73  28-Mar-2015 ks

Now all record types are either IN or OUT, no longer INOUT.
Modified inferred memory implementations that read their content from
data files generated by the cross-compiler.
Program memory: program.mem
Data    memory: data.crc
File names and locations defined in CONSTANTS.VHD
Therefore, van_Naumann program memory access can now be tested in simulation.

*** uCore 1.72  26-Feb-2014 ks

f_debug and f_break added to the design.

*** uCore 1.71  13-Mar-2013 ks

Bug corrected in TIMES control in uCore.VHD: Don't decrement when
reading from program memory (prog_sel='1').

*** uCore 1.70  10-Mar-2013 ks

DELAY vector for 1..4 delay cycles replaced by DELAY signal.
Reset synchronisation moved to CLOCKS.VHD.
fm/mod re-activated, because with an unsigned divisor, / and /mod can
not be implemented properly.
FUNCTIONs uReg_xxx implemented in CONSTANTS.VHD. As a consequence,
<regname>_ADDR definitions could be disposed.
System clock input prepared for PLL to be added in CLOCKS.VHD.
REGISTERS.VHD disposed. Instead, the CTRL Register is implemented in
CORE.VHD.
Generation of external data memory control signals moved from DATA_MEMORY.
VHD to CORE.VHD. Decoding for external data memory made more
restrictive: No more address wrap-around.
Program memory can only be written (when VON_NEUMANN is true) while
booting.

*** uCore 1.66  20-Oct-2010 ks

SAT_ARITH as compiler switch for saturated arithmetic.
op_ADC does no longer produce SAT_ARITH in order to implement multi precision arithmetic.
op_SMULT and op_MULTL introduced when hardware multiplier available and therefore,
overflow can be detected on standard Forth * ( n1 n2 -- n3 ).
Alternative form of m/mod with unsigned divisor. Considerably simpler.
fm/mod preserved but commented out.

boot code in PROG_MEMORY.VHD augmented to switch from boot code to program memory 
proper on a branch to address zero. Now uCore is romable by loading the program
into the FPGAs configuration memory.

*** uCore 1.65  24-Sep-2010 ks

New way of setting bit wise writeable registers CTRL_REG and INT_REG.
Now "1 CTRL_REG !" sets and "1 invert CTRL_REG !" resets bit number 0 of
the ctrl-register. This is similar to the way the opcode ST_SET works.

*** uCore 1.64 13-Mar-2010 ks

new implementation of division steps.
udivs, div, udivl for unsigned divide
sdivs, div, sdivl for signed divide (floored)
Several instructions re-arranged for easier decoding.
CONSTANTS.VHD with additional commands, which control Forth interpretation.

*** uCore 1.63 19-Aug-2009 ks

Errors discovered in Overflow and Carry processing.
CRCS, LDIVS, UDIVS instructions re-arranged.

*** uCore 1.62 12-Aug-2009 ks

RDROP added as instruction.

C-BRANCH abandoned, instead ?dup-BRANCH implemented.
S-BRANCH and NS-BRANCH are also followed by a DROP cycle.
"0= IF", "?DUP IF", "0< IF", "0< 0= IF", "CARRY? IF", "OVFL? IF"
are optimized to use specific BRANCH instructions.

LESS? implemented for an efficient Macro: <  - less? ;
( : less? ( n1-n2 -- f )  0< ovfl? xor ; implemented as opcode).

*** uCore 1.61 10-Aug-2009 ks

Instructions DROL, DROR, +ST, I added.

ei!, di@ and r! instructions abandoned.
ST_SET can be used to set and reset status bits
#c, #ovfl, #ie, #iis in two cycles.

DROP_FLAG eliminated, 0=BRANCH and 0<>BRANCH are 2 cycle
instructions with an additional DROP. Then DROP has been
moved to BRA BOTH and therefore, condition NEVER could
be abandoned for C-BRANCH

*** uCore 1.60  9-Aug-2009 ks

The superfluous conditional calls and all exits but ?EXIT and 0=EXIT
have been abandoned and the opening space was used for a thorough 
reshuffle of the opcodes. 
In the tables in CONSTANTS.VHD and MICROCORE.FS
each opcode is marked with two characters, which are either
+ (push), 0, - (pop), ? (conditional)
The first for dstack, the second for rstack.
The reshuffling creates more consistency w.r.t.
the stack activity. This results in slightly better timing and density.

CARRY?, OVFL?, and 0< have been implemented to fetch the flags.

7 opcodes are unused.

*** uCore 1.54  8-Aug-2009 ks

dsp! changed. It now pops the new stack and therefore, fills
NOS with a new valid content and only one additional drop
is needed thereafer.

*** uCore 1.53  6-Aug-2009 ks

TIME? instruction added, time_exc abandoned
0DIVS moved into USR area.
CRC, TIMES moved.
TIMER full data_width

*** uCore 1.52  4-Aug-2009 ks

Semaphor register eliminated
EVENT and CC instruction abandoned
TUCK UNDER added in the special branch group
TIMES instead of CC instruction
User instructions regrouped.

*** uCore 1.51  1-Aug-2009 ks

?DUP, ROT, -ROT added in the special branch group
Some internal signals renamed for consistency.
User instructions regrouped.

*** uCore 1.50 26-Jul-2009 ks

Major restructuring of the code, no functional change.
All entities below uCore have been dissolved, which leaves
only one single instruction decoding process for easier modifyability.

*** uCore 1.43  9-Jul-2009 ks

TIMES instruction modified: It executes n-times and not at all 
when the count is zero.
 
*** uCore 1.42 15-Jun-2009 ks

CRC-step instruction added.
Symplification of internal-ram in FUNCTIONS.VHD

*** uCore 1.41 30-Mar-2009 ks

A general wait-state generator has been build into CLOCKS.VHD,
which allows to stretch phase_2 of a cycle.

*** uCore 1.40 4-Mar-2009 ks

INT, EXC and ?OVFL instructions moved into the USR group, coinciding with
the hardware vector address.

?DUP removed as instruction, because it is a 3 instruction macro. (zero not IF dup THEN)

NX-BRANCH moved out of the <cond> NONE BRA group into the NXT BOTH BRA group and therefor,
NZ-BRANCH can now be defined and therefore, "not IF" became possible.

*** uCore 1.34 1-Mar-2009 ks

Setting of s_iis-bit changed. It will be set when executing INT_OP.
New operators DI@ and EI! added with "register" INTFL in the register group.
STATUS@ changed, it reads real s_iis-bit state.
256/ and 256* replaced by pack and unpack

*** uCore 1.33 10-Feb-2009 ks

Version with Centronics interface as umbilical abandoned. 
Therefore, the top entity is now CORE.VHD and the testbench is BENCH.VHD

The logic of the BOOTING flip-flop in PROG_MEMORY.VHD has been inverted 
to become BOOTING_N, because the Lattice P&R-tool would not preset it
at "1" as needed.

TIME_REGISTER relocated from CLOCKS.VHD into INTERRUPT.VHD

SEL_PROG mechanism simplified to realise wait-state on program memory data access (van_neumann)

uBus implementation restructured to make it easier to extend. 
Some register name changes in CONSTANTS.VHD

ALU routed through uBus(0)

*** uCore 1.321 27-Apr-2008

uForth cross-compiler extended with GOTO, ?GOTO, 0=GOTO to support the 
LCC C-compiler.

*** uCore 1.32  24-Apr-2005

EVENT operator moved from USR to special BRA group.
semaphors(sema0) <= ctrl(c_sema0) connected to allow testing in coretest.f.
TYPE data_select defined in CONSTANTS.VHD and used in UBUS.VHD for better
tri-state bus synthesis.

*** uCore 1.31 from uCore1110 17-Apr-2005

#ticks_per_ms introduced in CONSTANTS.VHD to define the resolution of the TIMER.

uCore sub-cycle control to adapt to clk frequencies above internal uCore delays
using constants PHASE_1 and PHASE_2 in CONSTANTS.VHD

Status, Flags, Semaphors registers removed from uBus because single bits must be
writeable in different entities. (Synthesizer hitches)
Former STATUS_REC and CTRL_REC data structures abandoned.

Internal and/or External memories for both data and program. IO_ADDR and
PROG_ADDR external address signals kept by latches (CORE_XXX.VHD) when disabled
for the sake of low power consumption.

Debugger interface re-structured. Physical interface factored out.
Uart and Centronics interface implemented using file pairs
core_uart.vhd   / bench_uart.vhd  or
core_centro.vhd / bench_centro.vhd.

Use of ALIAS definitions for instruction fields and to make the code generally
more readable.

All uBus signal sources integrated into uBus record. uBus.sources is an array
of registers optimising for extensibility of the uBus data sources in a
multiplexed implementation, which is centralised at uBus.vhd.
Selection of uBus sources using integer Constants.
Both a multiplexed and a tri-state bus implementation can be selected
by setting constant TRI_STATE in CONSTANTS.VHD

IS_<regname> constants introduced to simplify writing to internal registers.

*256, /256 instructions added as op_UP and op_DOWN in the Mathstep-Operators
Group.

WITH_MULT implements single cycle multiply if multiply hardware resources are
available in the chosen FPGA.

The program memory may now be initialised during configuration using a boot
loader. During configuration, flip-flop "booting" is set to '1' using
synthesizer attribute "init" (see: PROG_MEMORY.VHD). When executing "0 NOP BRANCH"
(branch to the reset location) the system will leave "boot-mode" and execute
the program that has been loaded into program memory (both internal and/or
external) during the boot load phase.

TOR integrated into the system and IP register and instructions THREAD and
TOKEN abandoned. As a result, data and then program memory will not be
accessed consecutively any more, which cuts down the worst case delay.

Now flags@ reads back all status flags, including all interrupt sources unmasked.
    ints@ reads back only enabled interrupt flags.

Semaphors and Time registers integrated into INTERRUPT.VHD.
EVENT instruction implemented: Waiting for a maximum time (in NOS) or for a sema_event
(in TOS). When timed out, the carry bit is set.

Entities PROG_MEMORY.VHD and DATA_MEMORY.VHD implemented to factor out
specific memory implementations (internal/external).

Change of umbilical debugger protocol: no RTS signalling, message based with full
ack_handshake.

Bug in NEXT fixed (tor_zero condition in uBus.vhd)

Using uCore1110, which was derived from uCore1026 replaceing the centronics
debug interface by a uart interface.