#-- Synplicity, Inc.
#-- Version 7.0.2   
#-- Project file D:\technik\Microcore\uCore\synthesizer\uCore.prj
#-- Written on Sat Aug 08 20:24:12 2009


#add_file options
add_file -vhdl -lib work "../uCore/functions.vhd"
add_file -vhdl -lib work "../uCore/constants.vhd"
add_file -vhdl -lib work "../uCore/uCore.vhd"
add_file -vhdl -lib work "../uCore/clocks.vhd"
add_file -vhdl -lib work "../uCore/uart.vhd"
add_file -vhdl -lib work "../uCore/debugger.vhd"
add_file -vhdl -lib work "../uCore/bootload.VHD"
add_file -vhdl -lib work "../uCore/prog_memory.vhd"
add_file -vhdl -lib work "../uCore/data_memory.vhd"
add_file -vhdl -lib work "../uCore/core.vhd"

#reporting options

#implementation: "synthesizer"
impl -add synthesizer

#device options
set_option -technology SPARTAN2
set_option -part XC2S200
set_option -package PQ208
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 10.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -modular 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./uCore.edf"
impl -active "synthesizer"