############################################################################### # # # IAR Assembler V5.30.1.50284/W32 for MSP430 28/Apr/2012 03:06:22 # # Copyright 1996-2011 IAR Systems AB. # # # # Target option = MSP430 # # Source file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\4e-init430G2553.s43# # List file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\List\4e-init430G2553.lst# # Object file = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\Obj\4e-init430G2553.r43# # Command line = C:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\4e-init430G2553.s43 # # -OC:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\Obj\ # # -s+ -M<> -w+ # # -LC:\Dokumente und Einstellungen\All Users\Dokumente\4e4th\Release0.34\List\ # # -i -t8 -xD -r -D__MSP430G2553__ # # -IC:\Programme\IAR Systems\Embedded Workbench 6.0 Kickstart\430\INC\ # # # ############################################################################### 1 000000 ; ---------------------------------------------- ------------------------ 2 000000 ; 4e4th is a Forth based on CamelForth 3 000000 ; for the Texas Instruments MSP430 4 000000 ; 5 000000 ; This program is free software; you can redistribute it and/or modify 6 000000 ; it under the terms of the GNU General Public License as published by 7 000000 ; the Free Software Foundation; either version 3 of the License, or 8 000000 ; (at your option) any later version. 9 000000 ; 10 000000 ; This program is distributed in the hope that it will be useful, 11 000000 ; but WITHOUT ANY WARRANTY; without even the implied warranty of 12 000000 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 000000 ; GNU General Public License for more details. 14 000000 ; 15 000000 ; You should have received a copy of the GNU General Public License 16 000000 ; along with this program. If not, see . 17 000000 ; 18 000000 ; See LICENSE TERMS in Brads file readme.txt as well. 19 000000 20 000000 ; ---------------------------------------------- ------------------------ 21 000000 ; 4e-init430G2553.s43 - reset interupt service routine - MSP430G2553 22 000000 ; ---------------------------------------------- ------------------------ 23 000000 24 000000 ; CamelForth RAM memory map: 25 000000 ; UP User Pointer, 2 bytes 26 000000 ; UAREA User area, 32 bytes 27 000000 ; UAREA+20h HOLD area, 40 bytes, grows down from end 28 000000 ; UAREA+48h PAD buffer, 88 bytes, must follow HOLD area 29 000000 ; UAREA+A0h Parameter stack, 128 B, grows down from end 30 000000 ; UAREA+120h Return stack, 128 B, grows down from end 31 000000 ; UAREA+1A0h TIB Terminal Input Buffer, 88 bytes 32 000000 33 000000 ; Note all must be word-aligned. 34 000000 ; See also the definitions of U0, S0, and R0 in the "system variables & 35 000000 ; constants" area. A task w/o terminal input requires 200h bytes. 36 000000 ; Double all except TIB and PAD for 32-bit CPUs. 37 000000 38 000000 39 000000 ; RAM map 40 000000 ; name celles comment 41 000000 ; ----- 42 000010 UAREA_SIZE = 16 ; UAREA 32 bytes 43 000000 ; ----- 44 000000 ; | LSTACK: leave stack 45 000000 ; | grows up 46 000000 ; | 47 000000 ; V 48 000000 ; 128 bytes 49 000000 ; ^ 50 000000 ; | 51 000000 ; | grows down 52 000036 PSTACK_SIZE = 54 ; | PSTACK: top of parameter stack area. 53 000000 ; ----- 54 000000 ; 128 bytes 55 000000 ; ^ 56 000000 ; | 57 000000 ; | grows down 58 000036 RSTACK_SIZE = 54 ; | RSTACK: top of return stack area. 59 000000 60 000000 ; aligned buffers only required for terminal tasks. 61 000000 ; names bytes 62 000000 ; ^ 63 000000 ; | 64 000000 ; | grows down 65 000022 HOLD_SIZE = 34 ; | HOLDAREA: 66 000000 ; ----- 67 000054 PAD_SIZE = 84 ; scratch pad 68 000000 ; ----- 69 000054 TIB_SIZE = 84 ; terminal input buffer 70 000000 ; ----- 71 000000 72 000000 ; PUBLIC UP,UAREA,PADAREA,LSTACK,PSTACK, RSTACK 73 000000 PUBLIC PADAREA,LSTACK,PSTACK,RSTACK 74 000000 PUBLIC TIBAREA,TIB_SIZE,UAREA_SIZE 75 000000 PUBLIC reset,main 76 000000 PUBLIC UAREA,UP,cor 77 000000 PUBLIC ROMDICT,RAMDICT 78 000000 79 000000 EXTERN lastword,fenceadr,NOOP 80 000000 ; EXTERN runmagic,runsmal 81 000000 EXTERN lastword 82 000000 EXTERN COLDIP,BOOTIP 83 000000 ; EXTERN DEBUGIP 84 000000 85 000000 RSEG DATA16_Z ; uninitialized RAM segment 86 000000 87 000000 ; RAM user area - system label, holds active user area 88 000000 ; initialiesed by BOOT 89 000000 ; see hilvl UINIT 90 000000 91 000000 UP: DS16 1 92 000002 UAREA: DS16 UAREA_SIZE 93 000022 94 000022 ; cor - cause of reset variable, copy of IFG1 95 000022 cor: DS16 1 96 000024 97 000024 ; LSTACK - start leave stack 98 000024 LSTACK: 99 000024 DS16 PSTACK_SIZE ; allocate parameter stack 100 000090 ; PSTACK - top of parameter stack 101 000090 PSTACK: 102 000090 DS16 RSTACK_SIZE ; allocate return stack 103 0000FC ; RSTACK - top of return stack 104 0000FC RSTACK: 105 0000FC DS8 HOLD_SIZE ; allocate hold area 106 00011E ; HOLDAREA - top of hold adrea 107 00011E HOLDAREA: 108 00011E 109 00011E ; PADAREA - start scratch pad; must follow HOLDAREA 110 00011E PADAREA: DS8 PAD_SIZE 111 000172 112 000172 ; TIBAREA - start Terminal Input Buffer 113 000172 TIBAREA: DS8 TIB_SIZE 114 0001C6 115 0001C6 ; RAMDICT - end of system areas, start of free RAM 116 0001C6 RAMDICT: 117 0001C6 118 0001C6 ; ---------------------------------------------- ------------------------ 119 0001C6 ; POWER ON RESET AND INITIALIZATION 120 0001C6 121 0001C6 #include "msp430G2553.h" ; #define controlled include file 1 0001C6 /*********************************************** ********************* 2 0001C6 * 3 0001C6 * Standard register and bit definitions for the Texas Instruments 4 0001C6 * MSP430 microcontroller. 5 0001C6 * 6 0001C6 * This file supports assembler and C development for 7 0001C6 * MSP430G2553 devices. 8 0001C6 * 9 0001C6 * Texas Instruments, Version 1.0 10 0001C6 * 11 0001C6 * Rev. 1.0, Setup 12 0001C6 * 13 0001C6 ************************************************ ********************/ 14 0001C6 15 0001C6 #ifndef __MSP430G2553 16 0001C6 #define __MSP430G2553 17 0001C6 18 0001C6 #ifdef __IAR_SYSTEMS_ICC__ 19 0001C6 #ifndef _SYSTEM_BUILD 20 0001C6 #pragma system_include 21 0001C6 #endif 22 0001C6 #endif 23 0001C6 24 0001C6 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */ 25 0001C6 #error msp430g2553.h file for use with ICC430/A430 only 26 0001C6 #endif 27 0001C6 28 0001C6 29 0001C6 #ifdef __IAR_SYSTEMS_ICC__ 30 0001C6 #include "in430.h" 31 0001C6 #pragma language=extended 33 0001C6 #define DEFC(name, address) __no_init volatile unsigned char name @ address; 34 0001C6 #define DEFW(name, address) __no_init volatile unsigned short name @ address; 35 0001C6 #define DEFXC volatile unsigned char 36 0001C6 #define DEFXW volatile unsigned short 38 0001C6 #endif /* __IAR_SYSTEMS_ICC__ */ 39 0001C6 40 0001C6 41 0001C6 #ifdef __IAR_SYSTEMS_ASM__ 42 0001C6 #define DEFC(name, address) sfrb name = address; 43 0001C6 #define DEFW(name, address) sfrw name = address; 44 0001C6 45 0001C6 #endif /* __IAR_SYSTEMS_ASM__*/ 46 0001C6 47 0001C6 #ifdef __cplusplus 48 0001C6 #define READ_ONLY 49 0001C6 #else 50 0001C6 #define READ_ONLY const 51 0001C6 #endif 52 0001C6 53 0001C6 /*********************************************** ************* 54 0001C6 * STANDARD BITS 55 0001C6 ************************************************ ************/ 56 0001C6 57 0001C6 #define BIT0 (0x0001u) 58 0001C6 #define BIT1 (0x0002u) 59 0001C6 #define BIT2 (0x0004u) 60 0001C6 #define BIT3 (0x0008u) 61 0001C6 #define BIT4 (0x0010u) 62 0001C6 #define BIT5 (0x0020u) 63 0001C6 #define BIT6 (0x0040u) 64 0001C6 #define BIT7 (0x0080u) 65 0001C6 #define BIT8 (0x0100u) 66 0001C6 #define BIT9 (0x0200u) 67 0001C6 #define BITA (0x0400u) 68 0001C6 #define BITB (0x0800u) 69 0001C6 #define BITC (0x1000u) 70 0001C6 #define BITD (0x2000u) 71 0001C6 #define BITE (0x4000u) 72 0001C6 #define BITF (0x8000u) 73 0001C6 74 0001C6 /*********************************************** ************* 75 0001C6 * STATUS REGISTER BITS 76 0001C6 ************************************************ ************/ 77 0001C6 78 0001C6 #define C (0x0001u) 79 0001C6 #define Z (0x0002u) 80 0001C6 #define N (0x0004u) 81 0001C6 #define V (0x0100u) 82 0001C6 #define GIE (0x0008u) 83 0001C6 #define CPUOFF (0x0010u) 84 0001C6 #define OSCOFF (0x0020u) 85 0001C6 #define SCG0 (0x0040u) 86 0001C6 #define SCG1 (0x0080u) 87 0001C6 88 0001C6 /* Low Power Modes coded with Bits 4-7 in SR */ 89 0001C6 90 0001C6 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */ 91 0001C6 #define LPM0 (CPUOFF) 92 0001C6 #define LPM1 (SCG0+CPUOFF) 93 0001C6 #define LPM2 (SCG1+CPUOFF) 94 0001C6 #define LPM3 (SCG1+SCG0+CPUOFF) 95 0001C6 #define LPM4 (SCG1+SCG0+OSCOFF+CP UOFF) 96 0001C6 /* End #defines for assembler */ 97 0001C6 98 0001C6 #else /* Begin #defines for C */ 99 0001C6 #define LPM0_bits (CPUOFF) 100 0001C6 #define LPM1_bits (SCG0+CPUOFF) 101 0001C6 #define LPM2_bits (SCG1+CPUOFF) 102 0001C6 #define LPM3_bits (SCG1+SCG0+CPUOFF) 103 0001C6 #define LPM4_bits (SCG1+SCG0+OSCOFF+CP UOFF) 105 0001C6 #include "in430.h" 107 0001C6 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ 108 0001C6 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */ 109 0001C6 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ 110 0001C6 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */ 111 0001C6 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ 112 0001C6 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */ 113 0001C6 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */ 114 0001C6 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */ 115 0001C6 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ 116 0001C6 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */ 117 0001C6 #endif /* End #defines for C */ 118 0001C6 119 0001C6 /*********************************************** ************* 120 0001C6 * PERIPHERAL FILE MAP 121 0001C6 ************************************************ ************/ 122 0001C6 123 0001C6 /*********************************************** ************* 124 0001C6 * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS 125 0001C6 ************************************************ ************/ 126 0001C6 127 0001C6 #define IE1_ (0x0000u) /* Interrupt Enable 1 */ 128 0001C6 DEFC( IE1 , IE1_) 129 000000 #define WDTIE (0x01) /* Watchdog Interrupt Enable */ 130 0001C6 #define OFIE (0x02) /* Osc. Fault Interrupt Enable */ 131 0001C6 #define NMIIE (0x10) /* NMI Interrupt Enable */ 132 0001C6 #define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */ 133 0001C6 134 0001C6 #define IFG1_ (0x0002u) /* Interrupt Flag 1 */ 135 0001C6 DEFC( IFG1 , IFG1_) 136 000000 #define WDTIFG (0x01) /* Watchdog Interrupt Flag */ 137 0001C6 #define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ 138 0001C6 #define PORIFG (0x04) /* Power On Interrupt Flag */ 139 0001C6 #define RSTIFG (0x08) /* Reset Interrupt Flag */ 140 0001C6 #define NMIIFG (0x10) /* NMI Interrupt Flag */ 141 0001C6 142 0001C6 #define IE2_ (0x0001u) /* Interrupt Enable 2 */ 143 0001C6 DEFC( IE2 , IE2_) 144 000000 #define UC0IE IE2 145 0001C6 #define UCA0RXIE (0x01) 146 0001C6 #define UCA0TXIE (0x02) 147 0001C6 #define UCB0RXIE (0x04) 148 0001C6 #define UCB0TXIE (0x08) 149 0001C6 150 0001C6 #define IFG2_ (0x0003u) /* Interrupt Flag 2 */ 151 0001C6 DEFC( IFG2 , IFG2_) 152 000000 #define UC0IFG IFG2 153 0001C6 #define UCA0RXIFG (0x01) 154 0001C6 #define UCA0TXIFG (0x02) 155 0001C6 #define UCB0RXIFG (0x04) 156 0001C6 #define UCB0TXIFG (0x08) 157 0001C6 158 0001C6 /*********************************************** ************* 159 0001C6 * ADC10 160 0001C6 ************************************************ ************/ 161 0001C6 #define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */ 162 0001C6 163 0001C6 #define ADC10DTC0_ (0x0048u) /* ADC10 Data Transfer Control 0 */ 164 0001C6 DEFC( ADC10DTC0 , ADC10DTC0_) 165 000000 #define ADC10DTC1_ (0x0049u) /* ADC10 Data Transfer Control 1 */ 166 0001C6 DEFC( ADC10DTC1 , ADC10DTC1_) 167 000000 #define ADC10AE0_ (0x004Au) /* ADC10 Analog Enable 0 */ 168 0001C6 DEFC( ADC10AE0 , ADC10AE0_) 169 000000 170 0001C6 #define ADC10CTL0_ (0x01B0u) /* ADC10 Control 0 */ 171 0001C6 DEFW( ADC10CTL0 , ADC10CTL0_) 172 000000 #define ADC10CTL1_ (0x01B2u) /* ADC10 Control 1 */ 173 0001C6 DEFW( ADC10CTL1 , ADC10CTL1_) 174 000000 #define ADC10MEM_ (0x01B4u) /* ADC10 Memory */ 175 0001C6 DEFW( ADC10MEM , ADC10MEM_) 176 000000 #define ADC10SA_ (0x01BCu) /* ADC10 Data Transfer Start Address */ 177 0001C6 DEFW( ADC10SA , ADC10SA_) 178 000000 179 0001C6 /* ADC10CTL0 */ 180 0001C6 #define ADC10SC (0x001) /* ADC10 Start Conversion */ 181 0001C6 #define ENC (0x002) /* ADC10 Enable Conversion */ 182 0001C6 #define ADC10IFG (0x004) /* ADC10 Interrupt Flag */ 183 0001C6 #define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */ 184 0001C6 #define ADC10ON (0x010) /* ADC10 On/Enable */ 185 0001C6 #define REFON (0x020) /* ADC10 Reference on */ 186 0001C6 #define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */ 187 0001C6 #define MSC (0x080) /* ADC10 Multiple SampleConversion */ 188 0001C6 #define REFBURST (0x100) /* ADC10 Reference Burst Mode */ 189 0001C6 #define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */ 190 0001C6 #define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */ 191 0001C6 #define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */ 192 0001C6 #define ADC10SHT1 (0x1000u) /* ADC10 Sample Hold Select Bit: 1 */ 193 0001C6 #define SREF0 (0x2000u) /* ADC10 Reference Select Bit: 0 */ 194 0001C6 #define SREF1 (0x4000u) /* ADC10 Reference Select Bit: 1 */ 195 0001C6 #define SREF2 (0x8000u) /* ADC10 Reference Select Bit: 2 */ 196 0001C6 #define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */ 197 0001C6 #define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */ 198 0001C6 #define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */ 199 0001C6 #define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */ 200 0001C6 201 0001C6 #define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */ 202 0001C6 #define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */ 203 0001C6 #define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */ 204 0001C6 #define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */ 205 0001C6 #define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */ 206 0001C6 #define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */ 207 0001C6 #define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ 208 0001C6 #define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ 209 0001C6 210 0001C6 /* ADC10CTL1 */ 211 0001C6 #define ADC10BUSY (0x0001u) /* ADC10 BUSY */ 212 0001C6 #define CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */ 213 0001C6 #define CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */ 214 0001C6 #define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select Bit: 0 */ 215 0001C6 #define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select Bit: 1 */ 216 0001C6 #define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select Bit: 0 */ 217 0001C6 #define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select Bit: 1 */ 218 0001C6 #define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select Bit: 2 */ 219 0001C6 #define ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */ 220 0001C6 #define ADC10DF (0x0200u) /* ADC10 Data Format 0:binary 1:2's complement */ 221 0001C6 #define SHS0 (0x0400u) /* ADC10 Sample/Hold Source Bit: 0 */ 222 0001C6 #define SHS1 (0x0800u) /* ADC10 Sample/Hold Source Bit: 1 */ 223 0001C6 #define INCH0 (0x1000u) /* ADC10 Input Channel Select Bit: 0 */ 224 0001C6 #define INCH1 (0x2000u) /* ADC10 Input Channel Select Bit: 1 */ 225 0001C6 #define INCH2 (0x4000u) /* ADC10 Input Channel Select Bit: 2 */ 226 0001C6 #define INCH3 (0x8000u) /* ADC10 Input Channel Select Bit: 3 */ 227 0001C6 228 0001C6 #define CONSEQ_0 (0*2u) /* Single channel single conversion */ 229 0001C6 #define CONSEQ_1 (1*2u) /* Sequence of channels */ 230 0001C6 #define CONSEQ_2 (2*2u) /* Repeat single channel */ 231 0001C6 #define CONSEQ_3 (3*2u) /* Repeat sequence of channels */ 232 0001C6 233 0001C6 #define ADC10SSEL_0 (0*8u) /* ADC10OSC */ 234 0001C6 #define ADC10SSEL_1 (1*8u) /* ACLK */ 235 0001C6 #define ADC10SSEL_2 (2*8u) /* MCLK */ 236 0001C6 #define ADC10SSEL_3 (3*8u) /* SMCLK */ 237 0001C6 238 0001C6 #define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */ 239 0001C6 #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */ 240 0001C6 #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */ 241 0001C6 #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */ 242 0001C6 #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */ 243 0001C6 #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */ 244 0001C6 #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */ 245 0001C6 #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */ 246 0001C6 247 0001C6 #define SHS_0 (0*0x400u) /* ADC10SC */ 248 0001C6 #define SHS_1 (1*0x400u) /* TA3 OUT1 */ 249 0001C6 #define SHS_2 (2*0x400u) /* TA3 OUT0 */ 250 0001C6 #define SHS_3 (3*0x400u) /* TA3 OUT2 */ 251 0001C6 252 0001C6 #define INCH_0 (0*0x1000u) /* Selects Channel 0 */ 253 0001C6 #define INCH_1 (1*0x1000u) /* Selects Channel 1 */ 254 0001C6 #define INCH_2 (2*0x1000u) /* Selects Channel 2 */ 255 0001C6 #define INCH_3 (3*0x1000u) /* Selects Channel 3 */ 256 0001C6 #define INCH_4 (4*0x1000u) /* Selects Channel 4 */ 257 0001C6 #define INCH_5 (5*0x1000u) /* Selects Channel 5 */ 258 0001C6 #define INCH_6 (6*0x1000u) /* Selects Channel 6 */ 259 0001C6 #define INCH_7 (7*0x1000u) /* Selects Channel 7 */ 260 0001C6 #define INCH_8 (8*0x1000u) /* Selects Channel 8 */ 261 0001C6 #define INCH_9 (9*0x1000u) /* Selects Channel 9 */ 262 0001C6 #define INCH_10 (10*0x1000u) /* Selects Channel 10 */ 263 0001C6 #define INCH_11 (11*0x1000u) /* Selects Channel 11 */ 264 0001C6 #define INCH_12 (12*0x1000u) /* Selects Channel 12 */ 265 0001C6 #define INCH_13 (13*0x1000u) /* Selects Channel 13 */ 266 0001C6 #define INCH_14 (14*0x1000u) /* Selects Channel 14 */ 267 0001C6 #define INCH_15 (15*0x1000u) /* Selects Channel 15 */ 268 0001C6 269 0001C6 /* ADC10DTC0 */ 270 0001C6 #define ADC10FETCH (0x001) /* This bit should normally be reset */ 271 0001C6 #define ADC10B1 (0x002) /* ADC10 block one */ 272 0001C6 #define ADC10CT (0x004) /* ADC10 continuous transfer */ 273 0001C6 #define ADC10TB (0x008) /* ADC10 two-block mode */ 274 0001C6 #define ADC10DISABLE (0x000) /* ADC10DTC1 */ 275 0001C6 276 0001C6 /*********************************************** ************* 277 0001C6 * Basic Clock Module 278 0001C6 ************************************************ ************/ 279 0001C6 #define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ 280 0001C6 281 0001C6 #define DCOCTL_ (0x0056u) /* DCO Clock Frequency Control */ 282 0001C6 DEFC( DCOCTL , DCOCTL_) 283 000000 #define BCSCTL1_ (0x0057u) /* Basic Clock System Control 1 */ 284 0001C6 DEFC( BCSCTL1 , BCSCTL1_) 285 000000 #define BCSCTL2_ (0x0058u) /* Basic Clock System Control 2 */ 286 0001C6 DEFC( BCSCTL2 , BCSCTL2_) 287 000000 #define BCSCTL3_ (0x0053u) /* Basic Clock System Control 3 */ 288 0001C6 DEFC( BCSCTL3 , BCSCTL3_) 289 000000 290 0001C6 #define MOD0 (0x01) /* Modulation Bit 0 */ 291 0001C6 #define MOD1 (0x02) /* Modulation Bit 1 */ 292 0001C6 #define MOD2 (0x04) /* Modulation Bit 2 */ 293 0001C6 #define MOD3 (0x08) /* Modulation Bit 3 */ 294 0001C6 #define MOD4 (0x10) /* Modulation Bit 4 */ 295 0001C6 #define DCO0 (0x20) /* DCO Select Bit 0 */ 296 0001C6 #define DCO1 (0x40) /* DCO Select Bit 1 */ 297 0001C6 #define DCO2 (0x80) /* DCO Select Bit 2 */ 298 0001C6 299 0001C6 #define RSEL0 (0x01) /* Range Select Bit 0 */ 300 0001C6 #define RSEL1 (0x02) /* Range Select Bit 1 */ 301 0001C6 #define RSEL2 (0x04) /* Range Select Bit 2 */ 302 0001C6 #define RSEL3 (0x08) /* Range Select Bit 3 */ 303 0001C6 #define DIVA0 (0x10) /* ACLK Divider 0 */ 304 0001C6 #define DIVA1 (0x20) /* ACLK Divider 1 */ 305 0001C6 #define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ 306 0001C6 #define XT2OFF (0x80) /* Enable XT2CLK */ 307 0001C6 308 0001C6 #define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ 309 0001C6 #define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ 310 0001C6 #define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ 311 0001C6 #define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ 312 0001C6 313 0001C6 #define DIVS0 (0x02) /* SMCLK Divider 0 */ 314 0001C6 #define DIVS1 (0x04) /* SMCLK Divider 1 */ 315 0001C6 #define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ 316 0001C6 #define DIVM0 (0x10) /* MCLK Divider 0 */ 317 0001C6 #define DIVM1 (0x20) /* MCLK Divider 1 */ 318 0001C6 #define SELM0 (0x40) /* MCLK Source Select 0 */ 319 0001C6 #define SELM1 (0x80) /* MCLK Source Select 1 */ 320 0001C6 321 0001C6 #define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ 322 0001C6 #define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ 323 0001C6 #define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ 324 0001C6 #define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ 325 0001C6 326 0001C6 #define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ 327 0001C6 #define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ 328 0001C6 #define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ 329 0001C6 #define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ 330 0001C6 331 0001C6 #define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ 332 0001C6 #define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ 333 0001C6 #define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ 334 0001C6 #define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ 335 0001C6 336 0001C6 #define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */ 337 0001C6 #define XT2OF (0x02) /* High frequency oscillator 2 fault flag */ 338 0001C6 #define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ 339 0001C6 #define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ 340 0001C6 #define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */ 341 0001C6 #define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */ 342 0001C6 #define XT2S0 (0x40) /* Mode 0 for XT2 */ 343 0001C6 #define XT2S1 (0x80) /* Mode 1 for XT2 */ 344 0001C6 345 0001C6 #define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */ 346 0001C6 #define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */ 347 0001C6 #define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */ 348 0001C6 #define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */ 349 0001C6 350 0001C6 #define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ 351 0001C6 #define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */ 352 0001C6 #define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */ 353 0001C6 #define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */ 354 0001C6 355 0001C6 #define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ 356 0001C6 #define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */ 357 0001C6 #define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */ 358 0001C6 #define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */ 359 0001C6 360 0001C6 /*********************************************** ************* 361 0001C6 * Comparator A 362 0001C6 ************************************************ ************/ 363 0001C6 #define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */ 364 0001C6 365 0001C6 #define CACTL1_ (0x0059u) /* Comparator A Control 1 */ 366 0001C6 DEFC( CACTL1 , CACTL1_) 367 000000 #define CACTL2_ (0x005Au) /* Comparator A Control 2 */ 368 0001C6 DEFC( CACTL2 , CACTL2_) 369 000000 #define CAPD_ (0x005Bu) /* Comparator A Port Disable */ 370 0001C6 DEFC( CAPD , CAPD_) 371 000000 372 0001C6 #define CAIFG (0x01) /* Comp. A Interrupt Flag */ 373 0001C6 #define CAIE (0x02) /* Comp. A Interrupt Enable */ 374 0001C6 #define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ 375 0001C6 #define CAON (0x08) /* Comp. A enable */ 376 0001C6 #define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ 377 0001C6 #define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ 378 0001C6 #define CARSEL (0x40) /* Comp. A Internal Reference Enable */ 379 0001C6 #define CAEX (0x80) /* Comp. A Exchange Inputs */ 380 0001C6 381 0001C6 #define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ 382 0001C6 #define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ 383 0001C6 #define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ 384 0001C6 #define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ 385 0001C6 386 0001C6 #define CAOUT (0x01) /* Comp. A Output */ 387 0001C6 #define CAF (0x02) /* Comp. A Enable Output Filter */ 388 0001C6 #define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */ 389 0001C6 #define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */ 390 0001C6 #define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */ 391 0001C6 #define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */ 392 0001C6 #define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */ 393 0001C6 #define CASHORT (0x80) /* Comp. A Short + and - Terminals */ 394 0001C6 395 0001C6 #define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ 396 0001C6 #define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ 397 0001C6 #define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ 398 0001C6 #define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ 399 0001C6 #define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ 400 0001C6 #define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ 401 0001C6 #define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ 402 0001C6 #define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ 403 0001C6 404 0001C6 /*********************************************** ************** 405 0001C6 * Flash Memory 406 0001C6 ************************************************ *************/ 407 0001C6 #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ 408 0001C6 409 0001C6 #define FCTL1_ (0x0128u) /* FLASH Control 1 */ 410 0001C6 DEFW( FCTL1 , FCTL1_) 411 000000 #define FCTL2_ (0x012Au) /* FLASH Control 2 */ 412 0001C6 DEFW( FCTL2 , FCTL2_) 413 000000 #define FCTL3_ (0x012Cu) /* FLASH Control 3 */ 414 0001C6 DEFW( FCTL3 , FCTL3_) 415 000000 416 0001C6 #define FRKEY (0x9600u) /* Flash key returned by read */ 417 0001C6 #define FWKEY (0xA500u) /* Flash key for write */ 418 0001C6 #define FXKEY (0x3300u) /* for use with XOR instruction */ 419 0001C6 420 0001C6 #define ERASE (0x0002u) /* Enable bit for Flash segment erase */ 421 0001C6 #define MERAS (0x0004u) /* Enable bit for Flash mass erase */ 422 0001C6 #define WRT (0x0040u) /* Enable bit for Flash write */ 423 0001C6 #define BLKWRT (0x0080u) /* Enable bit for Flash segment write */ 424 0001C6 #define SEGWRT (0x0080u) /* old definition */ /* Enable bit for Flash segment write */ 425 0001C6 426 0001C6 #define FN0 (0x0001u) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ 427 0001C6 #define FN1 (0x0002u) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ 428 0001C6 #ifndef FN2 429 0001C6 #define FN2 (0x0004u) 430 0001C6 #endif 431 0001C6 #ifndef FN3 432 0001C6 #define FN3 (0x0008u) 433 0001C6 #endif 434 0001C6 #ifndef FN4 435 0001C6 #define FN4 (0x0010u) 436 0001C6 #endif 437 0001C6 #define FN5 (0x0020u) 438 0001C6 #define FSSEL0 (0x0040u) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ 439 0001C6 #define FSSEL1 (0x0080u) /* Flash clock select 1 */ 440 0001C6 441 0001C6 #define FSSEL_0 (0x0000u) /* Flash clock select: 0 - ACLK */ 442 0001C6 #define FSSEL_1 (0x0040u) /* Flash clock select: 1 - MCLK */ 443 0001C6 #define FSSEL_2 (0x0080u) /* Flash clock select: 2 - SMCLK */ 444 0001C6 #define FSSEL_3 (0x00C0u) /* Flash clock select: 3 - SMCLK */ 445 0001C6 446 0001C6 #define BUSY (0x0001u) /* Flash busy: 1 */ 447 0001C6 #define KEYV (0x0002u) /* Flash Key violation flag */ 448 0001C6 #define ACCVIFG (0x0004u) /* Flash Access violation flag */ 449 0001C6 #define WAIT (0x0008u) /* Wait flag for segment write */ 450 0001C6 #define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */ 451 0001C6 #define EMEX (0x0020u) /* Flash Emergency Exit */ 452 0001C6 #define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ 453 0001C6 #define FAIL (0x0080u) /* Last Program or Erase failed */ 454 0001C6 455 0001C6 /*********************************************** ************* 456 0001C6 * DIGITAL I/O Port1/2 Pull up / Pull down Resistors 457 0001C6 ************************************************ ************/ 458 0001C6 #define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ 459 0001C6 #define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ 460 0001C6 461 0001C6 #define P1IN_ (0x0020u) /* Port 1 Input */ 462 0001C6 READ_ONLY DEFC( P1IN , P1IN_) 463 000000 #define P1OUT_ (0x0021u) /* Port 1 Output */ 464 0001C6 DEFC( P1OUT , P1OUT_) 465 000000 #define P1DIR_ (0x0022u) /* Port 1 Direction */ 466 0001C6 DEFC( P1DIR , P1DIR_) 467 000000 #define P1IFG_ (0x0023u) /* Port 1 Interrupt Flag */ 468 0001C6 DEFC( P1IFG , P1IFG_) 469 000000 #define P1IES_ (0x0024u) /* Port 1 Interrupt Edge Select */ 470 0001C6 DEFC( P1IES , P1IES_) 471 000000 #define P1IE_ (0x0025u) /* Port 1 Interrupt Enable */ 472 0001C6 DEFC( P1IE , P1IE_) 473 000000 #define P1SEL_ (0x0026u) /* Port 1 Selection */ 474 0001C6 DEFC( P1SEL , P1SEL_) 475 000000 #define P1SEL2_ (0x0041u) /* Port 1 Selection 2 */ 476 0001C6 DEFC( P1SEL2 , P1SEL2_) 477 000000 #define P1REN_ (0x0027u) /* Port 1 Resistor Enable */ 478 0001C6 DEFC( P1REN , P1REN_) 479 000000 480 0001C6 #define P2IN_ (0x0028u) /* Port 2 Input */ 481 0001C6 READ_ONLY DEFC( P2IN , P2IN_) 482 000000 #define P2OUT_ (0x0029u) /* Port 2 Output */ 483 0001C6 DEFC( P2OUT , P2OUT_) 484 000000 #define P2DIR_ (0x002Au) /* Port 2 Direction */ 485 0001C6 DEFC( P2DIR , P2DIR_) 486 000000 #define P2IFG_ (0x002Bu) /* Port 2 Interrupt Flag */ 487 0001C6 DEFC( P2IFG , P2IFG_) 488 000000 #define P2IES_ (0x002Cu) /* Port 2 Interrupt Edge Select */ 489 0001C6 DEFC( P2IES , P2IES_) 490 000000 #define P2IE_ (0x002Du) /* Port 2 Interrupt Enable */ 491 0001C6 DEFC( P2IE , P2IE_) 492 000000 #define P2SEL_ (0x002Eu) /* Port 2 Selection */ 493 0001C6 DEFC( P2SEL , P2SEL_) 494 000000 #define P2SEL2_ (0x0042u) /* Port 2 Selection 2 */ 495 0001C6 DEFC( P2SEL2 , P2SEL2_) 496 000000 #define P2REN_ (0x002Fu) /* Port 2 Resistor Enable */ 497 0001C6 DEFC( P2REN , P2REN_) 498 000000 499 0001C6 /*********************************************** ************* 500 0001C6 * DIGITAL I/O Port3 Pull up / Pull down Resistors 501 0001C6 ************************************************ ************/ 502 0001C6 #define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ 503 0001C6 504 0001C6 #define P3IN_ (0x0018u) /* Port 3 Input */ 505 0001C6 READ_ONLY DEFC( P3IN , P3IN_) 506 000000 #define P3OUT_ (0x0019u) /* Port 3 Output */ 507 0001C6 DEFC( P3OUT , P3OUT_) 508 000000 #define P3DIR_ (0x001Au) /* Port 3 Direction */ 509 0001C6 DEFC( P3DIR , P3DIR_) 510 000000 #define P3SEL_ (0x001Bu) /* Port 3 Selection */ 511 0001C6 DEFC( P3SEL , P3SEL_) 512 000000 #define P3SEL2_ (0x0043u) /* Port 3 Selection 2 */ 513 0001C6 DEFC( P3SEL2 , P3SEL2_) 514 000000 #define P3REN_ (0x0010u) /* Port 3 Resistor Enable */ 515 0001C6 DEFC( P3REN , P3REN_) 516 000000 517 0001C6 /*********************************************** ************* 518 0001C6 * Timer0_A3 519 0001C6 ************************************************ ************/ 520 0001C6 #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ 521 0001C6 522 0001C6 #define TA0IV_ (0x012Eu) /* Timer0_A3 Interrupt Vector Word */ 523 0001C6 READ_ONLY DEFW( TA0IV , TA0IV_) 524 000000 #define TA0CTL_ (0x0160u) /* Timer0_A3 Control */ 525 0001C6 DEFW( TA0CTL , TA0CTL_) 526 000000 #define TA0CCTL0_ (0x0162u) /* Timer0_A3 Capture/Compare Control 0 */ 527 0001C6 DEFW( TA0CCTL0 , TA0CCTL0_) 528 000000 #define TA0CCTL1_ (0x0164u) /* Timer0_A3 Capture/Compare Control 1 */ 529 0001C6 DEFW( TA0CCTL1 , TA0CCTL1_) 530 000000 #define TA0CCTL2_ (0x0166u) /* Timer0_A3 Capture/Compare Control 2 */ 531 0001C6 DEFW( TA0CCTL2 , TA0CCTL2_) 532 000000 #define TA0R_ (0x0170u) /* Timer0_A3 */ 533 0001C6 DEFW( TA0R , TA0R_) 534 000000 #define TA0CCR0_ (0x0172u) /* Timer0_A3 Capture/Compare 0 */ 535 0001C6 DEFW( TA0CCR0 , TA0CCR0_) 536 000000 #define TA0CCR1_ (0x0174u) /* Timer0_A3 Capture/Compare 1 */ 537 0001C6 DEFW( TA0CCR1 , TA0CCR1_) 538 000000 #define TA0CCR2_ (0x0176u) /* Timer0_A3 Capture/Compare 2 */ 539 0001C6 DEFW( TA0CCR2 , TA0CCR2_) 540 000000 541 0001C6 /* Alternate register names */ 542 0001C6 #define TAIV TA0IV /* Timer A Interrupt Vector Word */ 543 0001C6 #define TACTL TA0CTL /* Timer A Control */ 544 0001C6 #define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */ 545 0001C6 #define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */ 546 0001C6 #define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */ 547 0001C6 #define TAR TA0R /* Timer A */ 548 0001C6 #define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */ 549 0001C6 #define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */ 550 0001C6 #define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */ 551 0001C6 #define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */ 552 0001C6 #define TACTL_ TA0CTL_ /* Timer A Control */ 553 0001C6 #define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */ 554 0001C6 #define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */ 555 0001C6 #define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */ 556 0001C6 #define TAR_ TA0R_ /* Timer A */ 557 0001C6 #define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */ 558 0001C6 #define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */ 559 0001C6 #define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */ 560 0001C6 561 0001C6 /* Alternate register names 2 */ 562 0001C6 #define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ 563 0001C6 #define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ 564 0001C6 #define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ 565 0001C6 #define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ 566 0001C6 #define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ 567 0001C6 #define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ 568 0001C6 #define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ 569 0001C6 #define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ 570 0001C6 #define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ 571 0001C6 #define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ 572 0001C6 #define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ 573 0001C6 #define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ 574 0001C6 575 0001C6 #define TASSEL1 (0x0200u) /* Timer A clock source select 0 */ 576 0001C6 #define TASSEL0 (0x0100u) /* Timer A clock source select 1 */ 577 0001C6 #define ID1 (0x0080u) /* Timer A clock input divider 1 */ 578 0001C6 #define ID0 (0x0040u) /* Timer A clock input divider 0 */ 579 0001C6 #define MC1 (0x0020u) /* Timer A mode control 1 */ 580 0001C6 #define MC0 (0x0010u) /* Timer A mode control 0 */ 581 0001C6 #define TACLR (0x0004u) /* Timer A counter clear */ 582 0001C6 #define TAIE (0x0002u) /* Timer A counter interrupt enable */ 583 0001C6 #define TAIFG (0x0001u) /* Timer A counter interrupt flag */ 584 0001C6 585 0001C6 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ 586 0001C6 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ 587 0001C6 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */ 588 0001C6 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ 589 0001C6 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ 590 0001C6 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ 591 0001C6 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ 592 0001C6 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ 593 0001C6 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ 594 0001C6 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ 595 0001C6 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ 596 0001C6 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ 597 0001C6 598 0001C6 #define CM1 (0x8000u) /* Capture mode 1 */ 599 0001C6 #define CM0 (0x4000u) /* Capture mode 0 */ 600 0001C6 #define CCIS1 (0x2000u) /* Capture input select 1 */ 601 0001C6 #define CCIS0 (0x1000u) /* Capture input select 0 */ 602 0001C6 #define SCS (0x0800u) /* Capture sychronize */ 603 0001C6 #define SCCI (0x0400u) /* Latched capture signal (read) */ 604 0001C6 #define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ 605 0001C6 #define OUTMOD2 (0x0080u) /* Output mode 2 */ 606 0001C6 #define OUTMOD1 (0x0040u) /* Output mode 1 */ 607 0001C6 #define OUTMOD0 (0x0020u) /* Output mode 0 */ 608 0001C6 #define CCIE (0x0010u) /* Capture/compare interrupt enable */ 609 0001C6 #define CCI (0x0008u) /* Capture input signal (read) */ 610 0001C6 #define OUT (0x0004u) /* PWM Output signal if output mode 0 */ 611 0001C6 #define COV (0x0002u) /* Capture/compare overflow flag */ 612 0001C6 #define CCIFG (0x0001u) /* Capture/compare interrupt flag */ 613 0001C6 614 0001C6 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ 615 0001C6 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ 616 0001C6 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ 617 0001C6 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ 618 0001C6 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ 619 0001C6 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ 620 0001C6 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ 621 0001C6 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ 622 0001C6 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ 623 0001C6 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ 624 0001C6 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ 625 0001C6 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ 626 0001C6 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ 627 0001C6 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ 628 0001C6 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ 629 0001C6 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ 630 0001C6 631 0001C6 /* T0_A3IV Definitions */ 632 0001C6 #define TA0IV_NONE (0x0000u) /* No Interrupt pending */ 633 0001C6 #define TA0IV_TACCR1 (0x0002u) /* TA0CCR1_CCIFG */ 634 0001C6 #define TA0IV_TACCR2 (0x0004u) /* TA0CCR2_CCIFG */ 635 0001C6 #define TA0IV_6 (0x0006u) /* Reserved */ 636 0001C6 #define TA0IV_8 (0x0008u) /* Reserved */ 637 0001C6 #define TA0IV_TAIFG (0x000Au) /* TA0IFG */ 638 0001C6 639 0001C6 /*********************************************** ************* 640 0001C6 * Timer1_A3 641 0001C6 ************************************************ ************/ 642 0001C6 #define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ 643 0001C6 644 0001C6 #define TA1IV_ (0x011Eu) /* Timer1_A3 Interrupt Vector Word */ 645 0001C6 READ_ONLY DEFW( TA1IV , TA1IV_) 646 000000 #define TA1CTL_ (0x0180u) /* Timer1_A3 Control */ 647 0001C6 DEFW( TA1CTL , TA1CTL_) 648 000000 #define TA1CCTL0_ (0x0182u) /* Timer1_A3 Capture/Compare Control 0 */ 649 0001C6 DEFW( TA1CCTL0 , TA1CCTL0_) 650 000000 #define TA1CCTL1_ (0x0184u) /* Timer1_A3 Capture/Compare Control 1 */ 651 0001C6 DEFW( TA1CCTL1 , TA1CCTL1_) 652 000000 #define TA1CCTL2_ (0x0186u) /* Timer1_A3 Capture/Compare Control 2 */ 653 0001C6 DEFW( TA1CCTL2 , TA1CCTL2_) 654 000000 #define TA1R_ (0x0190u) /* Timer1_A3 */ 655 0001C6 DEFW( TA1R , TA1R_) 656 000000 #define TA1CCR0_ (0x0192u) /* Timer1_A3 Capture/Compare 0 */ 657 0001C6 DEFW( TA1CCR0 , TA1CCR0_) 658 000000 #define TA1CCR1_ (0x0194u) /* Timer1_A3 Capture/Compare 1 */ 659 0001C6 DEFW( TA1CCR1 , TA1CCR1_) 660 000000 #define TA1CCR2_ (0x0196u) /* Timer1_A3 Capture/Compare 2 */ 661 0001C6 DEFW( TA1CCR2 , TA1CCR2_) 662 000000 663 0001C6 /* Bits are already defined within the Timer0_Ax */ 664 0001C6 665 0001C6 /* T1_A3IV Definitions */ 666 0001C6 #define TA1IV_NONE (0x0000u) /* No Interrupt pending */ 667 0001C6 #define TA1IV_TACCR1 (0x0002u) /* TA1CCR1_CCIFG */ 668 0001C6 #define TA1IV_TACCR2 (0x0004u) /* TA1CCR2_CCIFG */ 669 0001C6 #define TA1IV_TAIFG (0x000Au) /* TA1IFG */ 670 0001C6 671 0001C6 /*********************************************** ************* 672 0001C6 * USCI 673 0001C6 ************************************************ ************/ 674 0001C6 #define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ 675 0001C6 676 0001C6 #define UCA0CTL0_ (0x0060u) /* USCI A0 Control Register 0 */ 677 0001C6 DEFC( UCA0CTL0 , UCA0CTL0_) 678 000000 #define UCA0CTL1_ (0x0061u) /* USCI A0 Control Register 1 */ 679 0001C6 DEFC( UCA0CTL1 , UCA0CTL1_) 680 000000 #define UCA0BR0_ (0x0062u) /* USCI A0 Baud Rate 0 */ 681 0001C6 DEFC( UCA0BR0 , UCA0BR0_) 682 000000 #define UCA0BR1_ (0x0063u) /* USCI A0 Baud Rate 1 */ 683 0001C6 DEFC( UCA0BR1 , UCA0BR1_) 684 000000 #define UCA0MCTL_ (0x0064u) /* USCI A0 Modulation Control */ 685 0001C6 DEFC( UCA0MCTL , UCA0MCTL_) 686 000000 #define UCA0STAT_ (0x0065u) /* USCI A0 Status Register */ 687 0001C6 DEFC( UCA0STAT , UCA0STAT_) 688 000000 #define UCA0RXBUF_ (0x0066u) /* USCI A0 Receive Buffer */ 689 0001C6 READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_) 690 000000 #define UCA0TXBUF_ (0x0067u) /* USCI A0 Transmit Buffer */ 691 0001C6 DEFC( UCA0TXBUF , UCA0TXBUF_) 692 000000 #define UCA0ABCTL_ (0x005Du) /* USCI A0 LIN Control */ 693 0001C6 DEFC( UCA0ABCTL , UCA0ABCTL_) 694 000000 #define UCA0IRTCTL_ (0x005Eu) /* USCI A0 IrDA Transmit Control */ 695 0001C6 DEFC( UCA0IRTCTL , UCA0IRTCTL_) 696 000000 #define UCA0IRRCTL_ (0x005Fu) /* USCI A0 IrDA Receive Control */ 697 0001C6 DEFC( UCA0IRRCTL , UCA0IRRCTL_) 698 000000 699 0001C6 700 0001C6 701 0001C6 #define UCB0CTL0_ (0x0068u) /* USCI B0 Control Register 0 */ 702 0001C6 DEFC( UCB0CTL0 , UCB0CTL0_) 703 000000 #define UCB0CTL1_ (0x0069u) /* USCI B0 Control Register 1 */ 704 0001C6 DEFC( UCB0CTL1 , UCB0CTL1_) 705 000000 #define UCB0BR0_ (0x006Au) /* USCI B0 Baud Rate 0 */ 706 0001C6 DEFC( UCB0BR0 , UCB0BR0_) 707 000000 #define UCB0BR1_ (0x006Bu) /* USCI B0 Baud Rate 1 */ 708 0001C6 DEFC( UCB0BR1 , UCB0BR1_) 709 000000 #define UCB0I2CIE_ (0x006Cu) /* USCI B0 I2C Interrupt Enable Register */ 710 0001C6 DEFC( UCB0I2CIE , UCB0I2CIE_) 711 000000 #define UCB0STAT_ (0x006Du) /* USCI B0 Status Register */ 712 0001C6 DEFC( UCB0STAT , UCB0STAT_) 713 000000 #define UCB0RXBUF_ (0x006Eu) /* USCI B0 Receive Buffer */ 714 0001C6 READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_) 715 000000 #define UCB0TXBUF_ (0x006Fu) /* USCI B0 Transmit Buffer */ 716 0001C6 DEFC( UCB0TXBUF , UCB0TXBUF_) 717 000000 #define UCB0I2COA_ (0x0118u) /* USCI B0 I2C Own Address */ 718 0001C6 DEFW( UCB0I2COA , UCB0I2COA_) 719 000000 #define UCB0I2CSA_ (0x011Au) /* USCI B0 I2C Slave Address */ 720 0001C6 DEFW( UCB0I2CSA , UCB0I2CSA_) 721 000000 722 0001C6 // UART-Mode Bits 723 0001C6 #define UCPEN (0x80) /* Async. Mode: Parity enable */ 724 0001C6 #define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ 725 0001C6 #define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ 726 0001C6 #define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ 727 0001C6 #define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ 728 0001C6 #define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ 729 0001C6 #define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ 730 0001C6 #define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ 731 0001C6 732 0001C6 // SPI-Mode Bits 733 0001C6 #define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ 734 0001C6 #define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ 735 0001C6 #define UCMST (0x08) /* Sync. Mode: Master Select */ 736 0001C6 737 0001C6 // I2C-Mode Bits 738 0001C6 #define UCA10 (0x80) /* 10-bit Address Mode */ 739 0001C6 #define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ 740 0001C6 #define UCMM (0x20) /* Multi-Master Environment */ 741 0001C6 //#define res (0x10) /* reserved */ 742 0001C6 #define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ 743 0001C6 #define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ 744 0001C6 #define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ 745 0001C6 #define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ 746 0001C6 747 0001C6 // UART-Mode Bits 748 0001C6 #define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ 749 0001C6 #define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ 750 0001C6 #define UCRXEIE (0x20) /* RX Error interrupt enable */ 751 0001C6 #define UCBRKIE (0x10) /* Break interrupt enable */ 752 0001C6 #define UCDORM (0x08) /* Dormant (Sleep) Mode */ 753 0001C6 #define UCTXADDR (0x04) /* Send next Data as Address */ 754 0001C6 #define UCTXBRK (0x02) /* Send next Data as Break */ 755 0001C6 #define UCSWRST (0x01) /* USCI Software Reset */ 756 0001C6 757 0001C6 // SPI-Mode Bits 758 0001C6 //#define res (0x20) /* reserved */ 759 0001C6 //#define res (0x10) /* reserved */ 760 0001C6 //#define res (0x08) /* reserved */ 761 0001C6 //#define res (0x04) /* reserved */ 762 0001C6 //#define res (0x02) /* reserved */ 763 0001C6 764 0001C6 // I2C-Mode Bits 765 0001C6 //#define res (0x20) /* reserved */ 766 0001C6 #define UCTR (0x10) /* Transmit/Receive Select/Flag */ 767 0001C6 #define UCTXNACK (0x08) /* Transmit NACK */ 768 0001C6 #define UCTXSTP (0x04) /* Transmit STOP */ 769 0001C6 #define UCTXSTT (0x02) /* Transmit START */ 770 0001C6 #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ 771 0001C6 #define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ 772 0001C6 #define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ 773 0001C6 #define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ 774 0001C6 775 0001C6 #define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ 776 0001C6 #define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ 777 0001C6 #define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ 778 0001C6 #define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ 779 0001C6 #define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ 780 0001C6 #define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ 781 0001C6 #define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ 782 0001C6 #define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ 783 0001C6 784 0001C6 #define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ 785 0001C6 #define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ 786 0001C6 #define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ 787 0001C6 #define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ 788 0001C6 #define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ 789 0001C6 #define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ 790 0001C6 #define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ 791 0001C6 #define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ 792 0001C6 #define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ 793 0001C6 #define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ 794 0001C6 #define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ 795 0001C6 #define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ 796 0001C6 #define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ 797 0001C6 #define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ 798 0001C6 #define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ 799 0001C6 #define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ 800 0001C6 801 0001C6 #define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ 802 0001C6 #define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ 803 0001C6 #define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ 804 0001C6 #define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ 805 0001C6 #define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ 806 0001C6 #define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ 807 0001C6 #define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ 808 0001C6 #define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ 809 0001C6 810 0001C6 #define UCLISTEN (0x80) /* USCI Listen mode */ 811 0001C6 #define UCFE (0x40) /* USCI Frame Error Flag */ 812 0001C6 #define UCOE (0x20) /* USCI Overrun Error Flag */ 813 0001C6 #define UCPE (0x10) /* USCI Parity Error Flag */ 814 0001C6 #define UCBRK (0x08) /* USCI Break received */ 815 0001C6 #define UCRXERR (0x04) /* USCI RX Error Flag */ 816 0001C6 #define UCADDR (0x02) /* USCI Address received Flag */ 817 0001C6 #define UCBUSY (0x01) /* USCI Busy Flag */ 818 0001C6 #define UCIDLE (0x02) /* USCI Idle line detected Flag */ 819 0001C6 820 0001C6 //#define res (0x80) /* reserved */ 821 0001C6 //#define res (0x40) /* reserved */ 822 0001C6 //#define res (0x20) /* reserved */ 823 0001C6 //#define res (0x10) /* reserved */ 824 0001C6 #define UCNACKIE (0x08) /* NACK Condition interrupt enable */ 825 0001C6 #define UCSTPIE (0x04) /* STOP Condition interrupt enable */ 826 0001C6 #define UCSTTIE (0x02) /* START Condition interrupt enable */ 827 0001C6 #define UCALIE (0x01) /* Arbitration Lost interrupt enable */ 828 0001C6 829 0001C6 #define UCSCLLOW (0x40) /* SCL low */ 830 0001C6 #define UCGC (0x20) /* General Call address received Flag */ 831 0001C6 #define UCBBUSY (0x10) /* Bus Busy Flag */ 832 0001C6 #define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ 833 0001C6 #define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ 834 0001C6 #define UCSTTIFG (0x02) /* START Condition interrupt Flag */ 835 0001C6 #define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ 836 0001C6 837 0001C6 #define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ 838 0001C6 #define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ 839 0001C6 #define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ 840 0001C6 #define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ 841 0001C6 #define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ 842 0001C6 #define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ 843 0001C6 #define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ 844 0001C6 #define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ 845 0001C6 846 0001C6 #define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ 847 0001C6 #define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ 848 0001C6 #define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ 849 0001C6 #define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ 850 0001C6 #define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ 851 0001C6 #define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ 852 0001C6 #define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ 853 0001C6 #define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ 854 0001C6 855 0001C6 //#define res (0x80) /* reserved */ 856 0001C6 //#define res (0x40) /* reserved */ 857 0001C6 #define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ 858 0001C6 #define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ 859 0001C6 #define UCSTOE (0x08) /* Sync-Field Timeout error */ 860 0001C6 #define UCBTOE (0x04) /* Break Timeout error */ 861 0001C6 //#define res (0x02) /* reserved */ 862 0001C6 #define UCABDEN (0x01) /* Auto Baud Rate detect enable */ 863 0001C6 864 0001C6 #define UCGCEN (0x8000u) /* I2C General Call enable */ 865 0001C6 #define UCOA9 (0x0200u) /* I2C Own Address 9 */ 866 0001C6 #define UCOA8 (0x0100u) /* I2C Own Address 8 */ 867 0001C6 #define UCOA7 (0x0080u) /* I2C Own Address 7 */ 868 0001C6 #define UCOA6 (0x0040u) /* I2C Own Address 6 */ 869 0001C6 #define UCOA5 (0x0020u) /* I2C Own Address 5 */ 870 0001C6 #define UCOA4 (0x0010u) /* I2C Own Address 4 */ 871 0001C6 #define UCOA3 (0x0008u) /* I2C Own Address 3 */ 872 0001C6 #define UCOA2 (0x0004u) /* I2C Own Address 2 */ 873 0001C6 #define UCOA1 (0x0002u) /* I2C Own Address 1 */ 874 0001C6 #define UCOA0 (0x0001u) /* I2C Own Address 0 */ 875 0001C6 876 0001C6 #define UCSA9 (0x0200u) /* I2C Slave Address 9 */ 877 0001C6 #define UCSA8 (0x0100u) /* I2C Slave Address 8 */ 878 0001C6 #define UCSA7 (0x0080u) /* I2C Slave Address 7 */ 879 0001C6 #define UCSA6 (0x0040u) /* I2C Slave Address 6 */ 880 0001C6 #define UCSA5 (0x0020u) /* I2C Slave Address 5 */ 881 0001C6 #define UCSA4 (0x0010u) /* I2C Slave Address 4 */ 882 0001C6 #define UCSA3 (0x0008u) /* I2C Slave Address 3 */ 883 0001C6 #define UCSA2 (0x0004u) /* I2C Slave Address 2 */ 884 0001C6 #define UCSA1 (0x0002u) /* I2C Slave Address 1 */ 885 0001C6 #define UCSA0 (0x0001u) /* I2C Slave Address 0 */ 886 0001C6 887 0001C6 /*********************************************** ************* 888 0001C6 * WATCHDOG TIMER 889 0001C6 ************************************************ ************/ 890 0001C6 #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ 891 0001C6 892 0001C6 #define WDTCTL_ (0x0120u) /* Watchdog Timer Control */ 893 0001C6 DEFW( WDTCTL , WDTCTL_) 894 000000 /* The bit names have been prefixed with "WDT" */ 895 0001C6 #define WDTIS0 (0x0001u) 896 0001C6 #define WDTIS1 (0x0002u) 897 0001C6 #define WDTSSEL (0x0004u) 898 0001C6 #define WDTCNTCL (0x0008u) 899 0001C6 #define WDTTMSEL (0x0010u) 900 0001C6 #define WDTNMI (0x0020u) 901 0001C6 #define WDTNMIES (0x0040u) 902 0001C6 #define WDTHOLD (0x0080u) 903 0001C6 904 0001C6 #define WDTPW (0x5A00u) 905 0001C6 906 0001C6 /* WDT-interval times [1ms] coded with Bits 0-2 */ 907 0001C6 /* WDT is clocked by fSMCLK (assumed 1MHz) */ 908 0001C6 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTC NTCL) /* 32ms interval (default) */ 909 0001C6 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTC NTCL+WDTIS0) /* 8ms " */ 910 0001C6 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTC NTCL+WDTIS1) /* 0.5ms " */ 911 0001C6 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTC NTCL+WDTIS1+WDTIS0) /* 0.064ms " */ 912 0001C6 /* WDT is clocked by fACLK (assumed 32KHz) */ 913 0001C6 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTC NTCL+WDTSSEL) /* 1000ms " */ 914 0001C6 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTC NTCL+WDTSSEL+WDTIS0) /* 250ms " */ 915 0001C6 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTC NTCL+WDTSSEL+WDTIS1) /* 16ms " */ 916 0001C6 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTC NTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ 917 0001C6 /* Watchdog mode -> reset after expired time */ 918 0001C6 /* WDT is clocked by fSMCLK (assumed 1MHz) */ 919 0001C6 #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ 920 0001C6 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTI S0) /* 8ms " */ 921 0001C6 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTI S1) /* 0.5ms " */ 922 0001C6 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTI S1+WDTIS0) /* 0.064ms " */ 923 0001C6 /* WDT is clocked by fACLK (assumed 32KHz) */ 924 0001C6 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTS SEL) /* 1000ms " */ 925 0001C6 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTS SEL+WDTIS0) /* 250ms " */ 926 0001C6 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTS SEL+WDTIS1) /* 16ms " */ 927 0001C6 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTS SEL+WDTIS1+WDTIS0) /* 1.9ms " */ 928 0001C6 929 0001C6 /* INTERRUPT CONTROL */ 930 0001C6 /* These two bits are defined in the Special Function Registers */ 931 0001C6 /* #define WDTIE 0x01 */ 932 0001C6 /* #define WDTIFG 0x01 */ 933 0001C6 934 0001C6 /*********************************************** ************* 935 0001C6 * Calibration Data in Info Mem 936 0001C6 ************************************************ ************/ 937 0001C6 938 0001C6 #ifndef __DisableCalData 939 0001C6 940 0001C6 #define CALDCO_16MHZ_ (0x10F8u) /* DCOCTL Calibration Data for 16MHz */ 941 0001C6 READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_ ) 942 000000 #define CALBC1_16MHZ_ (0x10F9u) /* BCSCTL1 Calibration Data for 16MHz */ 943 0001C6 READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_ ) 944 000000 #define CALDCO_12MHZ_ (0x10FAu) /* DCOCTL Calibration Data for 12MHz */ 945 0001C6 READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_ ) 946 000000 #define CALBC1_12MHZ_ (0x10FBu) /* BCSCTL1 Calibration Data for 12MHz */ 947 0001C6 READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_ ) 948 000000 #define CALDCO_8MHZ_ (0x10FCu) /* DCOCTL Calibration Data for 8MHz */ 949 0001C6 READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_) 950 000000 #define CALBC1_8MHZ_ (0x10FDu) /* BCSCTL1 Calibration Data for 8MHz */ 951 0001C6 READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_) 952 000000 #define CALDCO_1MHZ_ (0x10FEu) /* DCOCTL Calibration Data for 1MHz */ 953 0001C6 READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_) 954 000000 #define CALBC1_1MHZ_ (0x10FFu) /* BCSCTL1 Calibration Data for 1MHz */ 955 0001C6 READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_) 956 000000 957 0001C6 #endif /* #ifndef __DisableCalData */ 958 0001C6 959 0001C6 /*********************************************** ************* 960 0001C6 * Interrupt Vectors (offset from 0xFFE0) 961 0001C6 ************************************************ ************/ 962 0001C6 963 0001C6 #define PORT1_VECTOR (2 * 2u) /* 0xFFE4 Port 1 */ 964 0001C6 #define PORT2_VECTOR (3 * 2u) /* 0xFFE6 Port 2 */ 965 0001C6 #define ADC10_VECTOR (5 * 2u) /* 0xFFEA ADC10 */ 966 0001C6 #define USCIAB0TX_VECTOR (6 * 2u) /* 0xFFEC USCI A0/B0 Transmit */ 967 0001C6 #define USCIAB0RX_VECTOR (7 * 2u) /* 0xFFEE USCI A0/B0 Receive */ 968 0001C6 #define TIMER0_A1_VECTOR (8 * 2u) /* 0xFFF0 Timer0)A CC1, TA0 */ 969 0001C6 #define TIMER0_A0_VECTOR (9 * 2u) /* 0xFFF2 Timer0_A CC0 */ 970 0001C6 #define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */ 971 0001C6 #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */ 972 0001C6 #define TIMER1_A1_VECTOR (12 * 2u) /* 0xFFF8 Timer1_A CC1-4, TA1 */ 973 0001C6 #define TIMER1_A0_VECTOR (13 * 2u) /* 0xFFFA Timer1_A CC0 */ 974 0001C6 #define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */ 975 0001C6 #define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */ 976 0001C6 977 0001C6 /*********************************************** ************* 978 0001C6 * End of Modules 979 0001C6 ************************************************ ************/ 980 0001C6 #pragma language=default 981 0001C6 982 0001C6 #endif /* #ifndef __MSP430G2553 */ 983 0001C6 122 0001C6 #include "4e-CF430G2553forth.h" ; header macros and register defs 1 0001C6 ; ---------------------------------------------- ------------------------ 2 0001C6 ; 4e4th is a Forth based on CamelForth 3 0001C6 ; for the Texas Instruments MSP430 4 0001C6 ; 5 0001C6 ; This program is free software; you can redistribute it and/or modify 6 0001C6 ; it under the terms of the GNU General Public License as published by 7 0001C6 ; the Free Software Foundation; either version 3 of the License, or 8 0001C6 ; (at your option) any later version. 9 0001C6 ; 10 0001C6 ; This program is distributed in the hope that it will be useful, 11 0001C6 ; but WITHOUT ANY WARRANTY; without even the implied warranty of 12 0001C6 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 0001C6 ; GNU General Public License for more details. 14 0001C6 ; 15 0001C6 ; You should have received a copy of the GNU General Public License 16 0001C6 ; along with this program. If not, see . 17 0001C6 ; 18 0001C6 ; See LICENSE TERMS in Brads file readme.txt as well. 19 0001C6 20 0001C6 ; ---------------------------------------------- ------------------------ 21 0001C6 ; 4e-CF430G2553forth.h: - Register, Model, Macro declarations - MSP430G2553 22 0001C6 ; ---------------------------------------------- ------------------------ 23 0001C6 24 0001C6 // ; FORTH MEMORY USAGE 25 0001C6 // ; for Flash memory operations - this includes information and main 26 0001C6 // ; ROM, but not the main ROM used by the kernel (above E000h) 27 0001C6 #define INFOSTART (0x1000) // ok mk 28 0001C6 #define INFOEND (0x10FF) // ok mk 29 0001C6 #define RAMSTART (0x0200) // ok mk 30 0001C6 #define RAMEND (0x03FF) // ok mk 31 0001C6 #define FLASHSTART (0xC000) // ok mk 32 0001C6 #define FLASHEND (0xDFFF) // ok mk 33 0001C6 #define MAINSEG (512) // wozu ?? mk 34 0001C6 #define INFOSEG (128) // ?? mk 35 0001C6 36 0001C6 // ; FORTH REGISTER USAGE 37 0001C6 38 0001C6 // ; Forth virtual machine 39 0001C6 #define RSP SP 40 0001C6 #define PSP R4 41 0001C6 #define IP R5 42 0001C6 #define W R6 43 0001C6 #define TOS R7 44 0001C6 45 0001C6 // ; Loop parameters in registers 46 0001C6 #define INDEX R8 47 0001C6 #define LIMIT R9 48 0001C6 49 0001C6 // ; Scratch registers 50 0001C6 #define X R10 51 0001C6 #define Y R11 52 0001C6 #define Q R12 53 0001C6 #define T R13 54 0001C6 55 0001C6 // ; T.I. Integer Subroutines Definitions 56 0001C6 #define IROP1 TOS 57 0001C6 #define IROP2L R10 58 0001C6 #define IROP2M R11 59 0001C6 #define IRACL R12 60 0001C6 #define IRACM R13 61 0001C6 #define IRBT W 62 0001C6 63 0001C6 // ; INDIRECT-THREADED NEXT 64 0001C6 69 0001C6 70 0001C6 // ; BRANCH DESTINATION (RELATIVE BRANCH) 71 0001C6 // ; For relative branch addresses, i.e., a branch is ADD @IP,IP 72 0001C6 76 0001C6 77 0001C6 // ; HEADER CONSTRUCTION MACROS 78 0001C6 93 0001C6 102 0001C6 117 0001C6 123 0001C6 124 000000 RSEG CODE ; place program in 'CODE' segment 125 000000 126 000000 ; ---------------------------------------------- ------------------------ 127 000000 ; MSP430G2553 Initialize system 128 000000 ; (original: FR_EXP.lst and some of mecrisp (Koch) 129 000000 ; for LaunchPad 130 000000 131 000000 ; main - start_init, reset service routine 132 000000 main: ; Debugger requires the 'main' symbol. 133 000000 reset: ; forth requires the reset symbol. 134 000000 start_init: ; I require the start_init symbol. ;-) 135 000000 136 000000 B240805A2001 MOV.W #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer 137 000006 D2420200.... MOV.B &IFG1,&cor ; save IFG1 to cof low byte 138 00000C 139 00000C D242FD105700 mov.b &CALBC1_8MHZ, &BCSCTL1 ; Set DCO 140 000012 D242FC105600 mov.b &CALDCO_8MHZ, &DCOCTL ; to 8 MHz. 141 000018 142 000018 F24006002600 mov.b #006h, &P1SEL ; Use P1.1/P1.2 for USCI_A0 143 00001E F24006004100 mov.b #006h, &P1SEL2 ; Use P1.1/P1.2 for USCI_A0 144 000024 145 000024 ; Configure UART (Koch) 146 000024 F2D080006100 bis.b #UCSSEL_2,&UCA0CTL1 ;db2 SMCLK 147 00002A F24041006200 mov.b #65,&UCA0BR0 ;db3 8MHz 9600 Insgesamt 833 148 000030 F24003006300 mov.b #3,&UCA0BR1 ;db4 8MHz 9600 149 000036 E2426400 mov.b #UCBRS_2,&UCA0MCTL ;db5 Modulation UCBRSx = 2 150 00003A D2C36100 bic.b #UCSWRST,&UCA0CTL1 ;db6 **Initializ e USCI state machine** 151 00003E 152 00003E 153 00003E C2430000 clr.b &IE1 ; Lösche die Interrupt-Flags von Oscillator Fault, 154 000042 ; NMI, Flash-Violation. 155 000042 B24000A52801 mov.w #FWKEY, &FCTL1 ; Schreib- & Loeschzugr iffe ausgeschal tet. 156 000048 B24053A52A01 mov.w #FWKEY|FSSEL_1|19, &FCTL2 ; MCLK/20 for Flash Timing Generator 157 00004E 158 00004E B24010A52C01 mov.w #FWKEY+LOCK, &FCTL3 ; Lock Flash memory against writing 159 000054 160 000054 ; Enable port1 on Launchpad 161 000054 ; P1.0 = LED1 red 162 000054 ; P1.6 = LED2 green 163 000054 ; P1.3 = button 164 000054 ; P1.4 = free out (may be speaker+ ) 165 000054 ; P1.5 = free out (amy be speaker- ) 166 000054 F2D071002200 BIS.B #(BIT6+BIT5+BIT4+BIT0), &P1DIR 167 00005A F2D079002100 BIS.B #(BIT6+BIT5+BIT4+BIT3+BIT0), &P1OUT 168 000060 F2D22700 BIS.B #(BIT3),&P1REN ; pullup for S2 169 000064 170 000064 D243.... MOV.B #1,&(cor+1) ; hi byte 171 000068 172 000068 173 000068 ; setup forth registers 174 000068 3140.... MOV #RSTACK,SP ; set up return stack 175 00006C 3440.... MOV #PSTACK,PSP ; set up parameter stack 176 000070 B240........ MOV #UAREA,&UP ; initial user pointer 177 000076 3540.... MOV #BOOTIP,IP ; set IP of starting word 178 00007A ; MOV #COLDIP,IP ; set IP of starting word 179 00007A ; MOV #DEBUGIP,IP ; set IP of starting word 180 00007A 0743 MOV #0,TOS ; clear top of pstack 181 00007C NEXT 181.1 00007C 3645 MOV @IP+,W // ; fetch word address into W 181.2 00007E 3046 MOV @W+,PC // ; fetch code address into PC, W=PFA 181.3 000080 ENDM 182 000080 183 000080 init_end: 184 000080 185 000080 ; ---------------------------------------------- ------------------------ 186 000080 ; DEFAULT INTERRUPT HANDLER nullirq 187 000000 PUBLIC nullirq 188 000080 isr_start: 189 000080 0013 nullirq: RETI 190 000082 isr_end: 191 000082 192 000082 ROMDICT: 193 000082 END ACCVIE #define, value: (0x20), line: 132:1 ACCVIFG #define, value: (0x0004u), line: 448:1 ADC10AE0_ #define, value: (0x004Au), line: 167:1 168:1 ADC10B1 #define, value: (0x002), line: 271:1 ADC10BUSY #define, value: (0x0001u), line: 211:1 ADC10CT #define, value: (0x004), line: 272:1 ADC10CTL0_ #define, value: (0x01B0u), line: 170:1 171:1 ADC10CTL1_ #define, value: (0x01B2u), line: 172:1 173:1 ADC10DF #define, value: (0x0200u), line: 220:1 ADC10DISABLE #define, value: (0x000), line: 274:1 ADC10DIV0 #define, value: (0x0020u), line: 216:1 ADC10DIV1 #define, value: (0x0040u), line: 217:1 ADC10DIV2 #define, value: (0x0080u), line: 218:1 ADC10DIV_0 #define, value: (0*0x20u), line: 238:1 ADC10DIV_1 #define, value: (1*0x20u), line: 239:1 ADC10DIV_2 #define, value: (2*0x20u), line: 240:1 ADC10DIV_3 #define, value: (3*0x20u), line: 241:1 ADC10DIV_4 #define, value: (4*0x20u), line: 242:1 ADC10DIV_5 #define, value: (5*0x20u), line: 243:1 ADC10DIV_6 #define, value: (6*0x20u), line: 244:1 ADC10DIV_7 #define, value: (7*0x20u), line: 245:1 ADC10DTC0_ #define, value: (0x0048u), line: 163:1 164:1 ADC10DTC1_ #define, value: (0x0049u), line: 165:1 166:1 ADC10FETCH #define, value: (0x001), line: 270:1 ADC10IE #define, value: (0x008), line: 183:1 ADC10IFG #define, value: (0x004), line: 182:1 ADC10MEM_ #define, value: (0x01B4u), line: 174:1 175:1 ADC10ON #define, value: (0x010), line: 184:1 ADC10SA_ #define, value: (0x01BCu), line: 176:1 177:1 ADC10SC #define, value: (0x001), line: 180:1 ADC10SHT0 #define, value: (0x800), line: 191:1 ADC10SHT1 #define, value: (0x1000u), line: 192:1 ADC10SHT_0 #define, value: (0*0x800u), line: 196:1 ADC10SHT_1 #define, value: (1*0x800u), line: 197:1 ADC10SHT_2 #define, value: (2*0x800u), line: 198:1 ADC10SHT_3 #define, value: (3*0x800u), line: 199:1 ADC10SR #define, value: (0x400), line: 190:1 ADC10SSEL0 #define, value: (0x0008u), line: 214:1 ADC10SSEL1 #define, value: (0x0010u), line: 215:1 ADC10SSEL_0 #define, value: (0*8u), line: 233:1 ADC10SSEL_1 #define, value: (1*8u), line: 234:1 ADC10SSEL_2 #define, value: (2*8u), line: 235:1 ADC10SSEL_3 #define, value: (3*8u), line: 236:1 ADC10TB #define, value: (0x008), line: 273:1 ADC10_VECTOR #define, value: (5 * 2u), line: 965:1 BCSCTL1_ #define, value: (0x0057u), line: 283:1 284:1 BCSCTL2_ #define, value: (0x0058u), line: 285:1 286:1 BCSCTL3_ #define, value: (0x0053u), line: 287:1 288:1 BIT0 #define, value: (0x0001u), line: 57:1 166 167 BIT1 #define, value: (0x0002u), line: 58:1 BIT2 #define, value: (0x0004u), line: 59:1 BIT3 #define, value: (0x0008u), line: 60:1 167 168 BIT4 #define, value: (0x0010u), line: 61:1 166 167 BIT5 #define, value: (0x0020u), line: 62:1 166 167 BIT6 #define, value: (0x0040u), line: 63:1 166 167 BIT7 #define, value: (0x0080u), line: 64:1 BIT8 #define, value: (0x0100u), line: 65:1 BIT9 #define, value: (0x0200u), line: 66:1 BITA #define, value: (0x0400u), line: 67:1 BITB #define, value: (0x0800u), line: 68:1 BITC #define, value: (0x1000u), line: 69:1 BITD #define, value: (0x2000u), line: 70:1 BITE #define, value: (0x4000u), line: 71:1 BITF #define, value: (0x8000u), line: 72:1 BLKWRT #define, value: (0x0080u), line: 423:1 BUSY #define, value: (0x0001u), line: 446:1 C #define, value: (0x0001u), line: 78:1 CACTL1_ #define, value: (0x0059u), line: 365:1 366:1 CACTL2_ #define, value: (0x005Au), line: 367:1 368:1 CAEX #define, value: (0x80), line: 379:1 CAF #define, value: (0x02), line: 387:1 CAIE #define, value: (0x02), line: 373:1 CAIES #define, value: (0x04), line: 374:1 CAIFG #define, value: (0x01), line: 372:1 CALBC1_12MHZ_ #define, value: (0x10FBu), line: 946:1 947:1 CALBC1_16MHZ_ #define, value: (0x10F9u), line: 942:1 943:1 CALBC1_1MHZ_ #define, value: (0x10FFu), line: 954:1 955:1 CALBC1_8MHZ_ #define, value: (0x10FDu), line: 950:1 951:1 CALDCO_12MHZ_ #define, value: (0x10FAu), line: 944:1 945:1 CALDCO_16MHZ_ #define, value: (0x10F8u), line: 940:1 941:1 CALDCO_1MHZ_ #define, value: (0x10FEu), line: 952:1 953:1 CALDCO_8MHZ_ #define, value: (0x10FCu), line: 948:1 949:1 CAON #define, value: (0x08), line: 375:1 CAOUT #define, value: (0x01), line: 386:1 CAP #define, value: (0x0100u), line: 604:1 CAPD0 #define, value: (0x01), line: 395:1 CAPD1 #define, value: (0x02), line: 396:1 CAPD2 #define, value: (0x04), line: 397:1 CAPD3 #define, value: (0x08), line: 398:1 CAPD4 #define, value: (0x10), line: 399:1 CAPD5 #define, value: (0x20), line: 400:1 CAPD6 #define, value: (0x40), line: 401:1 CAPD7 #define, value: (0x80), line: 402:1 CAPD_ #define, value: (0x005Bu), line: 369:1 370:1 CAREF0 #define, value: (0x10), line: 376:1 CAREF1 #define, value: (0x20), line: 377:1 CAREF_0 #define, value: (0x00), line: 381:1 CAREF_1 #define, value: (0x10), line: 382:1 CAREF_2 #define, value: (0x20), line: 383:1 CAREF_3 #define, value: (0x30), line: 384:1 CARSEL #define, value: (0x40), line: 378:1 CASHORT #define, value: (0x80), line: 393:1 CCI #define, value: (0x0008u), line: 609:1 CCIE #define, value: (0x0010u), line: 608:1 CCIFG #define, value: (0x0001u), line: 612:1 CCIS0 #define, value: (0x1000u), line: 601:1 CCIS1 #define, value: (0x2000u), line: 600:1 CCIS_0 #define, value: (0*0x1000u), line: 622:1 CCIS_1 #define, value: (1*0x1000u), line: 623:1 CCIS_2 #define, value: (2*0x1000u), line: 624:1 CCIS_3 #define, value: (3*0x1000u), line: 625:1 CCR0 #define, value: TACCR0, line: 565:1 CCR0_ #define, value: TACCR0_, line: 571:1 CCR1 #define, value: TACCR1, line: 566:1 CCR1_ #define, value: TACCR1_, line: 572:1 CCR2 #define, value: TACCR2, line: 567:1 CCR2_ #define, value: TACCR2_, line: 573:1 CCTL0 #define, value: TACCTL0, line: 562:1 CCTL0_ #define, value: TACCTL0_, line: 568:1 CCTL1 #define, value: TACCTL1, line: 563:1 CCTL1_ #define, value: TACCTL1_, line: 569:1 CCTL2 #define, value: TACCTL2, line: 564:1 CCTL2_ #define, value: TACCTL2_, line: 570:1 CM0 #define, value: (0x4000u), line: 599:1 CM1 #define, value: (0x8000u), line: 598:1 CM_0 #define, value: (0*0x4000u), line: 626:1 CM_1 #define, value: (1*0x4000u), line: 627:1 CM_2 #define, value: (2*0x4000u), line: 628:1 CM_3 #define, value: (3*0x4000u), line: 629:1 COMPARATORA_VECTOR #define, value: (11 * 2u), line: 971:1 CONSEQ0 #define, value: (0x0002u), line: 212:1 CONSEQ1 #define, value: (0x0004u), line: 213:1 CONSEQ_0 #define, value: (0*2u), line: 228:1 CONSEQ_1 #define, value: (1*2u), line: 229:1 CONSEQ_2 #define, value: (2*2u), line: 230:1 CONSEQ_3 #define, value: (3*2u), line: 231:1 COV #define, value: (0x0002u), line: 611:1 CPUOFF #define, value: (0x0010u), line: 83:1 DCO0 #define, value: (0x20), line: 295:1 DCO1 #define, value: (0x40), line: 296:1 DCO2 #define, value: (0x80), line: 297:1 DCOCTL_ #define, value: (0x0056u), line: 281:1 282:1 DEFC #define, line: 42:1 128:1 135:1 143:1 151:1 164:1 166:1 168:1 282:1 284:1 286:1 288:1 366:1 368:1 370:1 462:1 464:1 466:1 468:1 470:1 472:1 474:1 476:1 478:1 481:1 483:1 485:1 487:1 489:1 491:1 493:1 495:1 497:1 505:1 507:1 509:1 511:1 513:1 515:1 677:1 679:1 681:1 683:1 685:1 687:1 689:1 691:1 693:1 695:1 697:1 702:1 704:1 706:1 708:1 710:1 712:1 714:1 716:1 941:1 943:1 945:1 947:1 949:1 951:1 953:1 955:1 DEFW #define, line: 43:1 171:1 173:1 175:1 177:1 410:1 412:1 414:1 523:1 525:1 527:1 529:1 531:1 533:1 535:1 537:1 539:1 645:1 647:1 649:1 651:1 653:1 655:1 657:1 659:1 661:1 718:1 720:1 893:1 DIVA0 #define, value: (0x10), line: 303:1 DIVA1 #define, value: (0x20), line: 304:1 DIVA_0 #define, value: (0x00), line: 308:1 DIVA_1 #define, value: (0x10), line: 309:1 DIVA_2 #define, value: (0x20), line: 310:1 DIVA_3 #define, value: (0x30), line: 311:1 DIVM0 #define, value: (0x10), line: 316:1 DIVM1 #define, value: (0x20), line: 317:1 DIVM_0 #define, value: (0x00), line: 326:1 DIVM_1 #define, value: (0x10), line: 327:1 DIVM_2 #define, value: (0x20), line: 328:1 DIVM_3 #define, value: (0x30), line: 329:1 DIVS0 #define, value: (0x02), line: 313:1 DIVS1 #define, value: (0x04), line: 314:1 DIVS_0 #define, value: (0x00), line: 321:1 DIVS_1 #define, value: (0x02), line: 322:1 DIVS_2 #define, value: (0x04), line: 323:1 DIVS_3 #define, value: (0x06), line: 324:1 EMEX #define, value: (0x0020u), line: 451:1 ENC #define, value: (0x002), line: 181:1 ERASE #define, value: (0x0002u), line: 420:1 FAIL #define, value: (0x0080u), line: 453:1 FCTL1_ #define, value: (0x0128u), line: 409:1 410:1 FCTL2_ #define, value: (0x012Au), line: 411:1 412:1 FCTL3_ #define, value: (0x012Cu), line: 413:1 414:1 FLASHEND #define, value: (0xDFFF), line: 32:2 FLASHSTART #define, value: (0xC000), line: 31:2 FN0 #define, value: (0x0001u), line: 426:1 FN1 #define, value: (0x0002u), line: 427:1 FN2 #define, value: (0x0004u), line: 429:1 FN3 #define, value: (0x0008u), line: 432:1 FN4 #define, value: (0x0010u), line: 435:1 FN5 #define, value: (0x0020u), line: 437:1 FRKEY #define, value: (0x9600u), line: 416:1 FSSEL0 #define, value: (0x0040u), line: 438:1 FSSEL1 #define, value: (0x0080u), line: 439:1 FSSEL_0 #define, value: (0x0000u), line: 441:1 FSSEL_1 #define, value: (0x0040u), line: 442:1 156 FSSEL_2 #define, value: (0x0080u), line: 443:1 FSSEL_3 #define, value: (0x00C0u), line: 444:1 FWKEY #define, value: (0xA500u), line: 417:1 155 156 158 FXKEY #define, value: (0x3300u), line: 418:1 GIE #define, value: (0x0008u), line: 82:1 ID0 #define, value: (0x0040u), line: 578:1 ID1 #define, value: (0x0080u), line: 577:1 ID_0 #define, value: (0*0x40u), line: 589:1 ID_1 #define, value: (1*0x40u), line: 590:1 ID_2 #define, value: (2*0x40u), line: 591:1 ID_3 #define, value: (3*0x40u), line: 592:1 IE1_ #define, value: (0x0000u), line: 127:1 128:1 IE2_ #define, value: (0x0001u), line: 142:1 143:1 IFG1_ #define, value: (0x0002u), line: 134:1 135:1 IFG2_ #define, value: (0x0003u), line: 150:1 151:1 INCH0 #define, value: (0x1000u), line: 223:1 INCH1 #define, value: (0x2000u), line: 224:1 INCH2 #define, value: (0x4000u), line: 225:1 INCH3 #define, value: (0x8000u), line: 226:1 INCH_0 #define, value: (0*0x1000u), line: 252:1 INCH_1 #define, value: (1*0x1000u), line: 253:1 INCH_10 #define, value: (10*0x1000u), line: 262:1 INCH_11 #define, value: (11*0x1000u), line: 263:1 INCH_12 #define, value: (12*0x1000u), line: 264:1 INCH_13 #define, value: (13*0x1000u), line: 265:1 INCH_14 #define, value: (14*0x1000u), line: 266:1 INCH_15 #define, value: (15*0x1000u), line: 267:1 INCH_2 #define, value: (2*0x1000u), line: 254:1 INCH_3 #define, value: (3*0x1000u), line: 255:1 INCH_4 #define, value: (4*0x1000u), line: 256:1 INCH_5 #define, value: (5*0x1000u), line: 257:1 INCH_6 #define, value: (6*0x1000u), line: 258:1 INCH_7 #define, value: (7*0x1000u), line: 259:1 INCH_8 #define, value: (8*0x1000u), line: 260:1 INCH_9 #define, value: (9*0x1000u), line: 261:1 INDEX #define, value: R8, line: 46:2 INFOEND #define, value: (0x10FF), line: 28:2 INFOSEG #define, value: (128), line: 34:2 INFOSTART #define, value: (0x1000), line: 27:2 IP #define, value: R5, line: 41:2 177 181 IRACL #define, value: R12, line: 59:2 IRACM #define, value: R13, line: 60:2 IRBT #define, value: W, line: 61:2 IROP1 #define, value: TOS, line: 56:2 IROP2L #define, value: R10, line: 57:2 IROP2M #define, value: R11, line: 58:2 ISSH #define, value: (0x0100u), line: 219:1 KEYV #define, value: (0x0002u), line: 447:1 LFXT1OF #define, value: (0x01), line: 336:1 LFXT1S0 #define, value: (0x10), line: 340:1 LFXT1S1 #define, value: (0x20), line: 341:1 LFXT1S_0 #define, value: (0x00), line: 350:1 LFXT1S_1 #define, value: (0x10), line: 351:1 LFXT1S_2 #define, value: (0x20), line: 352:1 LFXT1S_3 #define, value: (0x30), line: 353:1 LIMIT #define, value: R9, line: 47:2 LOCK #define, value: (0x0010u), line: 450:1 158 LOCKA #define, value: (0x0040u), line: 452:1 LPM0 #define, value: (CPUOFF), line: 91:1 LPM1 #define, value: (SCG0+CPUOFF), line: 92:1 LPM2 #define, value: (SCG1+CPUOFF), line: 93:1 LPM3 #define, value: (SCG1+SCG0+CPUOFF), line: 94:1 LPM4 #define, value: (SCG1+SCG0+OSCOFF+CPUOFF), line: 95:1 MAINSEG #define, value: (512), line: 33:2 MC0 #define, value: (0x0010u), line: 580:1 MC1 #define, value: (0x0020u), line: 579:1 MC_0 #define, value: (0*0x10u), line: 585:1 MC_1 #define, value: (1*0x10u), line: 586:1 MC_2 #define, value: (2*0x10u), line: 587:1 MC_3 #define, value: (3*0x10u), line: 588:1 MERAS #define, value: (0x0004u), line: 421:1 MOD0 #define, value: (0x01), line: 290:1 MOD1 #define, value: (0x02), line: 291:1 MOD2 #define, value: (0x04), line: 292:1 MOD3 #define, value: (0x08), line: 293:1 MOD4 #define, value: (0x10), line: 294:1 MSC #define, value: (0x080), line: 187:1 N #define, value: (0x0004u), line: 80:1 NMIIE #define, value: (0x10), line: 131:1 NMIIFG #define, value: (0x10), line: 140:1 NMI_VECTOR #define, value: (14 * 2u), line: 974:1 OFIE #define, value: (0x02), line: 130:1 OFIFG #define, value: (0x02), line: 137:1 OSCOFF #define, value: (0x0020u), line: 84:1 OUT #define, value: (0x0004u), line: 610:1 OUTMOD0 #define, value: (0x0020u), line: 607:1 OUTMOD1 #define, value: (0x0040u), line: 606:1 OUTMOD2 #define, value: (0x0080u), line: 605:1 OUTMOD_0 #define, value: (0*0x20u), line: 614:1 OUTMOD_1 #define, value: (1*0x20u), line: 615:1 OUTMOD_2 #define, value: (2*0x20u), line: 616:1 OUTMOD_3 #define, value: (3*0x20u), line: 617:1 OUTMOD_4 #define, value: (4*0x20u), line: 618:1 OUTMOD_5 #define, value: (5*0x20u), line: 619:1 OUTMOD_6 #define, value: (6*0x20u), line: 620:1 OUTMOD_7 #define, value: (7*0x20u), line: 621:1 P1DIR_ #define, value: (0x0022u), line: 465:1 466:1 P1IES_ #define, value: (0x0024u), line: 469:1 470:1 P1IE_ #define, value: (0x0025u), line: 471:1 472:1 P1IFG_ #define, value: (0x0023u), line: 467:1 468:1 P1IN_ #define, value: (0x0020u), line: 461:1 462:1 P1OUT_ #define, value: (0x0021u), line: 463:1 464:1 P1REN_ #define, value: (0x0027u), line: 477:1 478:1 P1SEL2_ #define, value: (0x0041u), line: 475:1 476:1 P1SEL_ #define, value: (0x0026u), line: 473:1 474:1 P2CA0 #define, value: (0x04), line: 388:1 P2CA1 #define, value: (0x08), line: 389:1 P2CA2 #define, value: (0x10), line: 390:1 P2CA3 #define, value: (0x20), line: 391:1 P2CA4 #define, value: (0x40), line: 392:1 P2DIR_ #define, value: (0x002Au), line: 484:1 485:1 P2IES_ #define, value: (0x002Cu), line: 488:1 489:1 P2IE_ #define, value: (0x002Du), line: 490:1 491:1 P2IFG_ #define, value: (0x002Bu), line: 486:1 487:1 P2IN_ #define, value: (0x0028u), line: 480:1 481:1 P2OUT_ #define, value: (0x0029u), line: 482:1 483:1 P2REN_ #define, value: (0x002Fu), line: 496:1 497:1 P2SEL2_ #define, value: (0x0042u), line: 494:1 495:1 P2SEL_ #define, value: (0x002Eu), line: 492:1 493:1 P3DIR_ #define, value: (0x001Au), line: 508:1 509:1 P3IN_ #define, value: (0x0018u), line: 504:1 505:1 P3OUT_ #define, value: (0x0019u), line: 506:1 507:1 P3REN_ #define, value: (0x0010u), line: 514:1 515:1 P3SEL2_ #define, value: (0x0043u), line: 512:1 513:1 P3SEL_ #define, value: (0x001Bu), line: 510:1 511:1 PORIFG #define, value: (0x04), line: 138:1 PORT1_VECTOR #define, value: (2 * 2u), line: 963:1 PORT2_VECTOR #define, value: (3 * 2u), line: 964:1 PSP #define, value: R4, line: 40:2 175 Q #define, value: R12, line: 52:2 RAMEND #define, value: (0x03FF), line: 30:2 RAMSTART #define, value: (0x0200), line: 29:2 READ_ONLY #define, value: const, line: 50:1 462:1 481:1 505:1 523:1 645:1 689:1 714:1 941:1 943:1 945:1 947:1 949:1 951:1 953:1 955:1 REF2_5V #define, value: (0x040), line: 186:1 REFBURST #define, value: (0x100), line: 188:1 REFON #define, value: (0x020), line: 185:1 REFOUT #define, value: (0x200), line: 189:1 RESET_VECTOR #define, value: (15 * 2u), line: 975:1 RSEL0 #define, value: (0x01), line: 299:1 RSEL1 #define, value: (0x02), line: 300:1 RSEL2 #define, value: (0x04), line: 301:1 RSEL3 #define, value: (0x08), line: 302:1 RSP #define, value: SP, line: 39:2 RSTIFG #define, value: (0x08), line: 139:1 SCCI #define, value: (0x0400u), line: 603:1 SCG0 #define, value: (0x0040u), line: 85:1 SCG1 #define, value: (0x0080u), line: 86:1 SCS #define, value: (0x0800u), line: 602:1 SEGWRT #define, value: (0x0080u), line: 424:1 SELM0 #define, value: (0x40), line: 318:1 SELM1 #define, value: (0x80), line: 319:1 SELM_0 #define, value: (0x00), line: 331:1 SELM_1 #define, value: (0x40), line: 332:1 SELM_2 #define, value: (0x80), line: 333:1 SELM_3 #define, value: (0xC0), line: 334:1 SELS #define, value: (0x08), line: 315:1 SHS0 #define, value: (0x0400u), line: 221:1 SHS1 #define, value: (0x0800u), line: 222:1 SHS_0 #define, value: (0*0x400u), line: 247:1 SHS_1 #define, value: (1*0x400u), line: 248:1 SHS_2 #define, value: (2*0x400u), line: 249:1 SHS_3 #define, value: (3*0x400u), line: 250:1 SREF0 #define, value: (0x2000u), line: 193:1 SREF1 #define, value: (0x4000u), line: 194:1 SREF2 #define, value: (0x8000u), line: 195:1 SREF_0 #define, value: (0*0x2000u), line: 201:1 SREF_1 #define, value: (1*0x2000u), line: 202:1 SREF_2 #define, value: (2*0x2000u), line: 203:1 SREF_3 #define, value: (3*0x2000u), line: 204:1 SREF_4 #define, value: (4*0x2000u), line: 205:1 SREF_5 #define, value: (5*0x2000u), line: 206:1 SREF_6 #define, value: (6*0x2000u), line: 207:1 SREF_7 #define, value: (7*0x2000u), line: 208:1 T #define, value: R13, line: 53:2 TA0CCR0_ #define, value: (0x0172u), line: 534:1 535:1 TA0CCR1_ #define, value: (0x0174u), line: 536:1 537:1 TA0CCR2_ #define, value: (0x0176u), line: 538:1 539:1 TA0CCTL0_ #define, value: (0x0162u), line: 526:1 527:1 TA0CCTL1_ #define, value: (0x0164u), line: 528:1 529:1 TA0CCTL2_ #define, value: (0x0166u), line: 530:1 531:1 TA0CTL_ #define, value: (0x0160u), line: 524:1 525:1 TA0IV_ #define, value: (0x012Eu), line: 522:1 523:1 TA0IV_6 #define, value: (0x0006u), line: 635:1 TA0IV_8 #define, value: (0x0008u), line: 636:1 TA0IV_NONE #define, value: (0x0000u), line: 632:1 TA0IV_TACCR1 #define, value: (0x0002u), line: 633:1 TA0IV_TACCR2 #define, value: (0x0004u), line: 634:1 TA0IV_TAIFG #define, value: (0x000Au), line: 637:1 TA0R_ #define, value: (0x0170u), line: 532:1 533:1 TA1CCR0_ #define, value: (0x0192u), line: 656:1 657:1 TA1CCR1_ #define, value: (0x0194u), line: 658:1 659:1 TA1CCR2_ #define, value: (0x0196u), line: 660:1 661:1 TA1CCTL0_ #define, value: (0x0182u), line: 648:1 649:1 TA1CCTL1_ #define, value: (0x0184u), line: 650:1 651:1 TA1CCTL2_ #define, value: (0x0186u), line: 652:1 653:1 TA1CTL_ #define, value: (0x0180u), line: 646:1 647:1 TA1IV_ #define, value: (0x011Eu), line: 644:1 645:1 TA1IV_NONE #define, value: (0x0000u), line: 666:1 TA1IV_TACCR1 #define, value: (0x0002u), line: 667:1 TA1IV_TACCR2 #define, value: (0x0004u), line: 668:1 TA1IV_TAIFG #define, value: (0x000Au), line: 669:1 TA1R_ #define, value: (0x0190u), line: 654:1 655:1 TACCR0 #define, value: TA0CCR0, line: 548:1 TACCR0_ #define, value: TA0CCR0_, line: 557:1 TACCR1 #define, value: TA0CCR1, line: 549:1 TACCR1_ #define, value: TA0CCR1_, line: 558:1 TACCR2 #define, value: TA0CCR2, line: 550:1 TACCR2_ #define, value: TA0CCR2_, line: 559:1 TACCTL0 #define, value: TA0CCTL0, line: 544:1 TACCTL0_ #define, value: TA0CCTL0_, line: 553:1 TACCTL1 #define, value: TA0CCTL1, line: 545:1 TACCTL1_ #define, value: TA0CCTL1_, line: 554:1 TACCTL2 #define, value: TA0CCTL2, line: 546:1 TACCTL2_ #define, value: TA0CCTL2_, line: 555:1 TACLR #define, value: (0x0004u), line: 581:1 TACTL #define, value: TA0CTL, line: 543:1 TACTL_ #define, value: TA0CTL_, line: 552:1 TAIE #define, value: (0x0002u), line: 582:1 TAIFG #define, value: (0x0001u), line: 583:1 TAIV #define, value: TA0IV, line: 542:1 TAIV_ #define, value: TA0IV_, line: 551:1 TAR #define, value: TA0R, line: 547:1 TAR_ #define, value: TA0R_, line: 556:1 TASSEL0 #define, value: (0x0100u), line: 576:1 TASSEL1 #define, value: (0x0200u), line: 575:1 TASSEL_0 #define, value: (0*0x100u), line: 593:1 TASSEL_1 #define, value: (1*0x100u), line: 594:1 TASSEL_2 #define, value: (2*0x100u), line: 595:1 TASSEL_3 #define, value: (3*0x100u), line: 596:1 TIMER0_A0_VECTOR #define, value: (9 * 2u), line: 969:1 TIMER0_A1_VECTOR #define, value: (8 * 2u), line: 968:1 TIMER1_A0_VECTOR #define, value: (13 * 2u), line: 973:1 TIMER1_A1_VECTOR #define, value: (12 * 2u), line: 972:1 TOS #define, value: R7, line: 43:2 180 UC0IE #define, value: IE2, line: 144:1 UC0IFG #define, value: IFG2, line: 152:1 UC7BIT #define, value: (0x10), line: 726:1 UCA0ABCTL_ #define, value: (0x005Du), line: 692:1 693:1 UCA0BR0_ #define, value: (0x0062u), line: 680:1 681:1 UCA0BR1_ #define, value: (0x0063u), line: 682:1 683:1 UCA0CTL0_ #define, value: (0x0060u), line: 676:1 677:1 UCA0CTL1_ #define, value: (0x0061u), line: 678:1 679:1 UCA0IRRCTL_ #define, value: (0x005Fu), line: 696:1 697:1 UCA0IRTCTL_ #define, value: (0x005Eu), line: 694:1 695:1 UCA0MCTL_ #define, value: (0x0064u), line: 684:1 685:1 UCA0RXBUF_ #define, value: (0x0066u), line: 688:1 689:1 UCA0RXIE #define, value: (0x01), line: 145:1 UCA0RXIFG #define, value: (0x01), line: 153:1 UCA0STAT_ #define, value: (0x0065u), line: 686:1 687:1 UCA0TXBUF_ #define, value: (0x0067u), line: 690:1 691:1 UCA0TXIE #define, value: (0x02), line: 146:1 UCA0TXIFG #define, value: (0x02), line: 154:1 UCA10 #define, value: (0x80), line: 738:1 UCABDEN #define, value: (0x01), line: 862:1 UCADDR #define, value: (0x02), line: 816:1 UCALIE #define, value: (0x01), line: 827:1 UCALIFG #define, value: (0x01), line: 835:1 UCB0BR0_ #define, value: (0x006Au), line: 705:1 706:1 UCB0BR1_ #define, value: (0x006Bu), line: 707:1 708:1 UCB0CTL0_ #define, value: (0x0068u), line: 701:1 702:1 UCB0CTL1_ #define, value: (0x0069u), line: 703:1 704:1 UCB0I2CIE_ #define, value: (0x006Cu), line: 709:1 710:1 UCB0I2COA_ #define, value: (0x0118u), line: 717:1 718:1 UCB0I2CSA_ #define, value: (0x011Au), line: 719:1 720:1 UCB0RXBUF_ #define, value: (0x006Eu), line: 713:1 714:1 UCB0RXIE #define, value: (0x04), line: 147:1 UCB0RXIFG #define, value: (0x04), line: 155:1 UCB0STAT_ #define, value: (0x006Du), line: 711:1 712:1 UCB0TXBUF_ #define, value: (0x006Fu), line: 715:1 716:1 UCB0TXIE #define, value: (0x08), line: 148:1 UCB0TXIFG #define, value: (0x08), line: 156:1 UCBBUSY #define, value: (0x10), line: 831:1 UCBRF0 #define, value: (0x10), line: 778:1 UCBRF1 #define, value: (0x20), line: 777:1 UCBRF2 #define, value: (0x40), line: 776:1 UCBRF3 #define, value: (0x80), line: 775:1 UCBRF_0 #define, value: (0x00), line: 784:1 UCBRF_1 #define, value: (0x10), line: 785:1 UCBRF_10 #define, value: (0xA0), line: 794:1 UCBRF_11 #define, value: (0xB0), line: 795:1 UCBRF_12 #define, value: (0xC0), line: 796:1 UCBRF_13 #define, value: (0xD0), line: 797:1 UCBRF_14 #define, value: (0xE0), line: 798:1 UCBRF_15 #define, value: (0xF0), line: 799:1 UCBRF_2 #define, value: (0x20), line: 786:1 UCBRF_3 #define, value: (0x30), line: 787:1 UCBRF_4 #define, value: (0x40), line: 788:1 UCBRF_5 #define, value: (0x50), line: 789:1 UCBRF_6 #define, value: (0x60), line: 790:1 UCBRF_7 #define, value: (0x70), line: 791:1 UCBRF_8 #define, value: (0x80), line: 792:1 UCBRF_9 #define, value: (0x90), line: 793:1 UCBRK #define, value: (0x08), line: 814:1 UCBRKIE #define, value: (0x10), line: 751:1 UCBRS0 #define, value: (0x02), line: 781:1 UCBRS1 #define, value: (0x04), line: 780:1 UCBRS2 #define, value: (0x08), line: 779:1 UCBRS_0 #define, value: (0x00), line: 801:1 UCBRS_1 #define, value: (0x02), line: 802:1 UCBRS_2 #define, value: (0x04), line: 803:1 149 UCBRS_3 #define, value: (0x06), line: 804:1 UCBRS_4 #define, value: (0x08), line: 805:1 UCBRS_5 #define, value: (0x0A), line: 806:1 UCBRS_6 #define, value: (0x0C), line: 807:1 UCBRS_7 #define, value: (0x0E), line: 808:1 UCBTOE #define, value: (0x04), line: 860:1 UCBUSY #define, value: (0x01), line: 817:1 UCCKPH #define, value: (0x80), line: 733:1 UCCKPL #define, value: (0x40), line: 734:1 UCDELIM0 #define, value: (0x10), line: 858:1 UCDELIM1 #define, value: (0x20), line: 857:1 UCDORM #define, value: (0x08), line: 752:1 UCFE #define, value: (0x40), line: 811:1 UCGC #define, value: (0x20), line: 830:1 UCGCEN #define, value: (0x8000u), line: 864:1 UCIDLE #define, value: (0x02), line: 818:1 UCIREN #define, value: (0x01), line: 844:1 UCIRRXFE #define, value: (0x01), line: 853:1 UCIRRXFL0 #define, value: (0x04), line: 851:1 UCIRRXFL1 #define, value: (0x08), line: 850:1 UCIRRXFL2 #define, value: (0x10), line: 849:1 UCIRRXFL3 #define, value: (0x20), line: 848:1 UCIRRXFL4 #define, value: (0x40), line: 847:1 UCIRRXFL5 #define, value: (0x80), line: 846:1 UCIRRXPL #define, value: (0x02), line: 852:1 UCIRTXCLK #define, value: (0x02), line: 843:1 UCIRTXPL0 #define, value: (0x04), line: 842:1 UCIRTXPL1 #define, value: (0x08), line: 841:1 UCIRTXPL2 #define, value: (0x10), line: 840:1 UCIRTXPL3 #define, value: (0x20), line: 839:1 UCIRTXPL4 #define, value: (0x40), line: 838:1 UCIRTXPL5 #define, value: (0x80), line: 837:1 UCLISTEN #define, value: (0x80), line: 810:1 UCMM #define, value: (0x20), line: 740:1 UCMODE0 #define, value: (0x02), line: 729:1 UCMODE1 #define, value: (0x04), line: 728:1 UCMODE_0 #define, value: (0x00), line: 742:1 UCMODE_1 #define, value: (0x02), line: 743:1 UCMODE_2 #define, value: (0x04), line: 744:1 UCMODE_3 #define, value: (0x06), line: 745:1 UCMSB #define, value: (0x20), line: 725:1 UCMST #define, value: (0x08), line: 735:1 UCNACKIE #define, value: (0x08), line: 824:1 UCNACKIFG #define, value: (0x08), line: 832:1 UCOA0 #define, value: (0x0001u), line: 874:1 UCOA1 #define, value: (0x0002u), line: 873:1 UCOA2 #define, value: (0x0004u), line: 872:1 UCOA3 #define, value: (0x0008u), line: 871:1 UCOA4 #define, value: (0x0010u), line: 870:1 UCOA5 #define, value: (0x0020u), line: 869:1 UCOA6 #define, value: (0x0040u), line: 868:1 UCOA7 #define, value: (0x0080u), line: 867:1 UCOA8 #define, value: (0x0100u), line: 866:1 UCOA9 #define, value: (0x0200u), line: 865:1 UCOE #define, value: (0x20), line: 812:1 UCOS16 #define, value: (0x01), line: 782:1 UCPAR #define, value: (0x40), line: 724:1 UCPE #define, value: (0x10), line: 813:1 UCPEN #define, value: (0x80), line: 723:1 UCRXEIE #define, value: (0x20), line: 750:1 UCRXERR #define, value: (0x04), line: 815:1 UCSA0 #define, value: (0x0001u), line: 885:1 UCSA1 #define, value: (0x0002u), line: 884:1 UCSA2 #define, value: (0x0004u), line: 883:1 UCSA3 #define, value: (0x0008u), line: 882:1 UCSA4 #define, value: (0x0010u), line: 881:1 UCSA5 #define, value: (0x0020u), line: 880:1 UCSA6 #define, value: (0x0040u), line: 879:1 UCSA7 #define, value: (0x0080u), line: 878:1 UCSA8 #define, value: (0x0100u), line: 877:1 UCSA9 #define, value: (0x0200u), line: 876:1 UCSCLLOW #define, value: (0x40), line: 829:1 UCSLA10 #define, value: (0x40), line: 739:1 UCSPB #define, value: (0x08), line: 727:1 UCSSEL0 #define, value: (0x40), line: 749:1 UCSSEL1 #define, value: (0x80), line: 748:1 UCSSEL_0 #define, value: (0x00), line: 770:1 UCSSEL_1 #define, value: (0x40), line: 771:1 UCSSEL_2 #define, value: (0x80), line: 772:1 146 UCSSEL_3 #define, value: (0xC0), line: 773:1 UCSTOE #define, value: (0x08), line: 859:1 UCSTPIE #define, value: (0x04), line: 825:1 UCSTPIFG #define, value: (0x04), line: 833:1 UCSTTIE #define, value: (0x02), line: 826:1 UCSTTIFG #define, value: (0x02), line: 834:1 UCSWRST #define, value: (0x01), line: 755:1 150 UCSYNC #define, value: (0x01), line: 730:1 UCTR #define, value: (0x10), line: 766:1 UCTXADDR #define, value: (0x04), line: 753:1 UCTXBRK #define, value: (0x02), line: 754:1 UCTXNACK #define, value: (0x08), line: 767:1 UCTXSTP #define, value: (0x04), line: 768:1 UCTXSTT #define, value: (0x02), line: 769:1 USCIAB0RX_VECTOR #define, value: (7 * 2u), line: 967:1 USCIAB0TX_VECTOR #define, value: (6 * 2u), line: 966:1 V #define, value: (0x0100u), line: 81:1 W #define, value: R6, line: 42:2 181 181 WAIT #define, value: (0x0008u), line: 449:1 WDTCNTCL #define, value: (0x0008u), line: 898:1 WDTCTL_ #define, value: (0x0120u), line: 892:1 893:1 WDTHOLD #define, value: (0x0080u), line: 902:1 136 WDTIE #define, value: (0x01), line: 129:1 WDTIFG #define, value: (0x01), line: 136:1 WDTIS0 #define, value: (0x0001u), line: 895:1 WDTIS1 #define, value: (0x0002u), line: 896:1 WDTNMI #define, value: (0x0020u), line: 900:1 WDTNMIES #define, value: (0x0040u), line: 901:1 WDTPW #define, value: (0x5A00u), line: 904:1 136 WDTSSEL #define, value: (0x0004u), line: 897:1 WDTTMSEL #define, value: (0x0010u), line: 899:1 WDT_ADLY_1000 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL), line: 913:1 WDT_ADLY_16 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1), line: 915:1 WDT_ADLY_1_9 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 916:1 WDT_ADLY_250 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0), line: 914:1 WDT_ARST_1000 #define, value: (WDTPW+WDTCNTCL+WDTSSEL), line: 924:1 WDT_ARST_16 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1), line: 926:1 WDT_ARST_1_9 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 927:1 WDT_ARST_250 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0), line: 925:1 WDT_MDLY_0_064 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0), line: 911:1 WDT_MDLY_0_5 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1), line: 910:1 WDT_MDLY_32 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL), line: 908:1 WDT_MDLY_8 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0), line: 909:1 WDT_MRST_0_064 #define, value: (WDTPW+WDTCNTCL+WDTIS1+WDTIS0), line: 922:1 WDT_MRST_0_5 #define, value: (WDTPW+WDTCNTCL+WDTIS1), line: 921:1 WDT_MRST_32 #define, value: (WDTPW+WDTCNTCL), line: 919:1 WDT_MRST_8 #define, value: (WDTPW+WDTCNTCL+WDTIS0), line: 920:1 WDT_VECTOR #define, value: (10 * 2u), line: 970:1 WRT #define, value: (0x0040u), line: 422:1 X #define, value: R10, line: 50:2 XCAP0 #define, value: (0x04), line: 338:1 XCAP1 #define, value: (0x08), line: 339:1 XCAP_0 #define, value: (0x00), line: 345:1 XCAP_1 #define, value: (0x04), line: 346:1 XCAP_2 #define, value: (0x08), line: 347:1 XCAP_3 #define, value: (0x0C), line: 348:1 XT2OF #define, value: (0x02), line: 337:1 XT2OFF #define, value: (0x80), line: 306:1 XT2S0 #define, value: (0x40), line: 342:1 XT2S1 #define, value: (0x80), line: 343:1 XT2S_0 #define, value: (0x00), line: 355:1 XT2S_1 #define, value: (0x40), line: 356:1 XT2S_2 #define, value: (0x80), line: 357:1 XT2S_3 #define, value: (0xC0), line: 358:1 XTS #define, value: (0x40), line: 305:1 Y #define, value: R11, line: 51:2 Z #define, value: (0x0002u), line: 79:1 __430X_CORE__ #define, value: 1, line: 0 __430_CORE__ #define, value: 0, line: 0 __A430__ #define, value: 1, line: 0 __BUILD_NUMBER__ #define, line: 0 __CORE__ #define, value: 0, line: 0 __DATE__ #define, line: 0 __FILE__ #define, line: 0 __IAR_SYSTEMS_ASM #define, line: 0 __IAR_SYSTEMS_ASM__ #define, line: 0 __LINE__ #define, line: 0 __MSP430G2553 #define, value: , line: 16:1 __MSP430G2553__ #define, value: 1, line: 0 __MSP430_HAS_ADC10__ #define, value: , line: 161:1 __MSP430_HAS_BC2__ #define, value: , line: 279:1 __MSP430_HAS_CAPLUS__ #define, value: , line: 363:1 __MSP430_HAS_FLASH2__ #define, value: , line: 407:1 __MSP430_HAS_PORT1_R__ #define, value: , line: 458:1 __MSP430_HAS_PORT2_R__ #define, value: , line: 459:1 __MSP430_HAS_PORT3_R__ #define, value: , line: 502:1 __MSP430_HAS_T1A3__ #define, value: , line: 642:1 __MSP430_HAS_TA3__ #define, value: , line: 520:1 __MSP430_HAS_USCI__ #define, value: , line: 674:1 __MSP430_HAS_WDT__ #define, value: , line: 890:1 __SUBVERSION__ #define, line: 0 __TID__ #define, line: 0 24:1 __TIME__ #define, line: 0 __VER__ #define, line: 0 Segment Type Mode ---------------------------------------- CODE UNTYPED REL DATA16_Z UNTYPED REL Label Mode Type Segment Value/Offset ------------------------------------------------------------------------------ ADC10AE0 ABS CONST UNTYP. ASEG 4A ADC10CTL0 ABS CONST UNTYP. ASEG 1B0 ADC10CTL1 ABS CONST UNTYP. ASEG 1B2 ADC10DTC0 ABS CONST UNTYP. ASEG 48 ADC10DTC1 ABS CONST UNTYP. ASEG 49 ADC10MEM ABS CONST UNTYP. ASEG 1B4 ADC10SA ABS CONST UNTYP. ASEG 1BC BCSCTL1 ABS CONST UNTYP. ASEG 57 BCSCTL2 ABS CONST UNTYP. ASEG 58 BCSCTL3 ABS CONST UNTYP. ASEG 53 BOOTIP ABS CONST EXT [000] UNTYP. __EXTERNS Solved Extern CACTL1 ABS CONST UNTYP. ASEG 59 CACTL2 ABS CONST UNTYP. ASEG 5A CALBC1_12MHZ ABS CONST UNTYP. ASEG 10FB CALBC1_16MHZ ABS CONST UNTYP. ASEG 10F9 CALBC1_1MHZ ABS CONST UNTYP. ASEG 10FF CALBC1_8MHZ ABS CONST UNTYP. ASEG 10FD CALDCO_12MHZ ABS CONST UNTYP. ASEG 10FA CALDCO_16MHZ ABS CONST UNTYP. ASEG 10F8 CALDCO_1MHZ ABS CONST UNTYP. ASEG 10FE CALDCO_8MHZ ABS CONST UNTYP. ASEG 10FC CAPD ABS CONST UNTYP. ASEG 5B COLDIP ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern DCOCTL ABS CONST UNTYP. ASEG 56 FCTL1 ABS CONST UNTYP. ASEG 128 FCTL2 ABS CONST UNTYP. ASEG 12A FCTL3 ABS CONST UNTYP. ASEG 12C HOLDAREA REL CONST UNTYP. DATA16_Z 11E HOLD_SIZE ABS CONST UNTYP. ASEG 22 IE1 ABS CONST UNTYP. ASEG 0 IE2 ABS CONST UNTYP. ASEG 1 IFG1 ABS CONST UNTYP. ASEG 2 IFG2 ABS CONST UNTYP. ASEG 3 LSTACK REL CONST PUB UNTYP. DATA16_Z 24 NOOP ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern P1DIR ABS CONST UNTYP. ASEG 22 P1IE ABS CONST UNTYP. ASEG 25 P1IES ABS CONST UNTYP. ASEG 24 P1IFG ABS CONST UNTYP. ASEG 23 P1IN ABS CONST UNTYP. ASEG 20 P1OUT ABS CONST UNTYP. ASEG 21 P1REN ABS CONST UNTYP. ASEG 27 P1SEL ABS CONST UNTYP. ASEG 26 P1SEL2 ABS CONST UNTYP. ASEG 41 P2DIR ABS CONST UNTYP. ASEG 2A P2IE ABS CONST UNTYP. ASEG 2D P2IES ABS CONST UNTYP. ASEG 2C P2IFG ABS CONST UNTYP. ASEG 2B P2IN ABS CONST UNTYP. ASEG 28 P2OUT ABS CONST UNTYP. ASEG 29 P2REN ABS CONST UNTYP. ASEG 2F P2SEL ABS CONST UNTYP. ASEG 2E P2SEL2 ABS CONST UNTYP. ASEG 42 P3DIR ABS CONST UNTYP. ASEG 1A P3IN ABS CONST UNTYP. ASEG 18 P3OUT ABS CONST UNTYP. ASEG 19 P3REN ABS CONST UNTYP. ASEG 10 P3SEL ABS CONST UNTYP. ASEG 1B P3SEL2 ABS CONST UNTYP. ASEG 43 PADAREA REL CONST PUB UNTYP. DATA16_Z 11E PAD_SIZE ABS CONST UNTYP. ASEG 54 PSTACK REL CONST PUB UNTYP. DATA16_Z 90 PSTACK_SIZE ABS CONST UNTYP. ASEG 36 RAMDICT REL CONST PUB UNTYP. DATA16_Z 1C6 ROMDICT REL CONST PUB UNTYP. CODE 82 RSTACK REL CONST PUB UNTYP. DATA16_Z FC RSTACK_SIZE ABS CONST UNTYP. ASEG 36 TA0CCR0 ABS CONST UNTYP. ASEG 172 TA0CCR1 ABS CONST UNTYP. ASEG 174 TA0CCR2 ABS CONST UNTYP. ASEG 176 TA0CCTL0 ABS CONST UNTYP. ASEG 162 TA0CCTL1 ABS CONST UNTYP. ASEG 164 TA0CCTL2 ABS CONST UNTYP. ASEG 166 TA0CTL ABS CONST UNTYP. ASEG 160 TA0IV ABS CONST UNTYP. ASEG 12E TA0R ABS CONST UNTYP. ASEG 170 TA1CCR0 ABS CONST UNTYP. ASEG 192 TA1CCR1 ABS CONST UNTYP. ASEG 194 TA1CCR2 ABS CONST UNTYP. ASEG 196 TA1CCTL0 ABS CONST UNTYP. ASEG 182 TA1CCTL1 ABS CONST UNTYP. ASEG 184 TA1CCTL2 ABS CONST UNTYP. ASEG 186 TA1CTL ABS CONST UNTYP. ASEG 180 TA1IV ABS CONST UNTYP. ASEG 11E TA1R ABS CONST UNTYP. ASEG 190 TIBAREA REL CONST PUB UNTYP. DATA16_Z 172 TIB_SIZE ABS CONST PUB UNTYP. ASEG 54 UAREA REL CONST PUB UNTYP. DATA16_Z 2 UAREA_SIZE ABS CONST PUB UNTYP. ASEG 10 UCA0ABCTL ABS CONST UNTYP. ASEG 5D UCA0BR0 ABS CONST UNTYP. ASEG 62 UCA0BR1 ABS CONST UNTYP. ASEG 63 UCA0CTL0 ABS CONST UNTYP. ASEG 60 UCA0CTL1 ABS CONST UNTYP. ASEG 61 UCA0IRRCTL ABS CONST UNTYP. ASEG 5F UCA0IRTCTL ABS CONST UNTYP. ASEG 5E UCA0MCTL ABS CONST UNTYP. ASEG 64 UCA0RXBUF ABS CONST UNTYP. ASEG 66 UCA0STAT ABS CONST UNTYP. ASEG 65 UCA0TXBUF ABS CONST UNTYP. ASEG 67 UCB0BR0 ABS CONST UNTYP. ASEG 6A UCB0BR1 ABS CONST UNTYP. ASEG 6B UCB0CTL0 ABS CONST UNTYP. ASEG 68 UCB0CTL1 ABS CONST UNTYP. ASEG 69 UCB0I2CIE ABS CONST UNTYP. ASEG 6C UCB0I2COA ABS CONST UNTYP. ASEG 118 UCB0I2CSA ABS CONST UNTYP. ASEG 11A UCB0RXBUF ABS CONST UNTYP. ASEG 6E UCB0STAT ABS CONST UNTYP. ASEG 6D UCB0TXBUF ABS CONST UNTYP. ASEG 6F UP REL CONST PUB UNTYP. DATA16_Z 0 WDTCTL ABS CONST UNTYP. ASEG 120 cor REL CONST PUB UNTYP. DATA16_Z 22 fenceadr ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern init_end REL CONST UNTYP. CODE 80 isr_end REL CONST UNTYP. CODE 82 isr_start REL CONST UNTYP. CODE 80 lastword ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern main REL CONST PUB UNTYP. CODE 0 nullirq REL CONST PUB UNTYP. CODE 80 reset REL CONST PUB UNTYP. CODE 0 start_init REL CONST UNTYP. CODE 0 ############################## # CRC:3464 # # Errors: 0 # # Warnings: 0 # # Bytes: 130 # ##############################